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priznat posted:A Palladium system? Those are pretty impressive, there is one at my work too but I have nothing to do with it so far. EDIT: This isn't really HDL/FPGA related, but it's close. Altium is starting to annoy my Hardware department (32-bit [even on a 64-bit platform] apparently single-threaded executable without any other subprocesses doing any additional work) when working on large, complex designs, but the price is right, and obviously there's a lot of sunk cost in the ~6+ years of ~60+ hour weeks our principal hardware engineer has put in to learning and being ridiculously productive with it. We're starting to evaluate possible other options; I'm looking at PADS VX right now (or I would be if I weren't still waiting for Mentor to send me a time-limited demo license because they're still in the 1980s with licensing), but what else should I/we consider? We don't care about auto-routing, we do care about DRC, consistently solid UI responsiveness, ability to handle really complex boards (rat's nest), layer counts, component counts, and (ideally but not required) polygons, at a roughly Altium-like price. minidracula fucked around with this message at 08:03 on Oct 3, 2014 |
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Oct 3, 2014 07:50
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minidracula posted:Can I borrow some free-of-charge runtime on that? Naw man I got it mining bitcoins  (not really but we joke about that. It's pretty much in use 24/7/365)
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Oct 3, 2014 08:16
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Quick design question, its not strictly Verilog specific: I am implementing a system on my FPGA that has numerous event providers that I want to forward to an USB connection. I have a FIFO to manage the USB data, but that only works for one connection. I don't want to do round robin polling since the events may come in bursts, so I'm not sure if I should use a small FIFO per event source, or if it is possible an advisable to create some sort of FIFO that lets me add up to N entries at a time in whatever order.
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Oct 8, 2014 00:00
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