Learning electronics: Release the Magic Blue Smoke

The Something Awful Forums > Discussion > Hobbies, Crafts, & Houses > Learning electronics: Release the Magic Blue Smoke

«‹›782 »

Corrupt Politician: Aug 8, 2007

Brekelefuw posted:

For programmability, I would like to have them flash in a pattern or two. The theme for one of the bands is New Orleans, and I wanted blue and white swirls like a hurricane to spin around the bell like a toilet flushes (bad explanation?)
Or I would like to put a solid logo up for the other band.
Sound reactivity would be good as well once I learn how to do the initial idea.
I guess I would need a controller to tell which pattern to go to etc.

That's a pretty complex pattern for 100+ LEDs. A microcontroller could certainly handle it, but programming the timing pattern for each LED individually is going to be a bitch and involve a lot of tedious trial and error. It might be worth it to set them up in a grid pattern and control them as a VGA screen or something, but I don't know too much about doing that or whether it would actually save enough work to be worth it.

# ? Jul 20, 2010 04:45

Adbot: ADBOT LOVES YOU

# ? Jun 3, 2024 17:04

blorpy: Jan 5, 2005

So, I have http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,398,525&Prod=FX12 and it's been sitting around for a while. I recently found the Milkymist project and started using their cores and found some of the stuff works pretty well. Of course, I eventually decided to finally tackle the DDR SDRAM on my board using their core for it. I have to say that this failed spectacularly. I'm getting all sorts of timing issues because I have no idea what the hell I'm actually doing.

I realized that I need to slow down and actually read something that will help me understand what's even going on here to begin with. I'm a senior in a computer engineering program so a lot of signal and logic stuff has been very familiar, but all this clock stuff has me rather confused. I've been reading the Virtex 4 user manual trying to understand what the clocking resources do but unfortunately I'm coming up rather short. In particular, I'm not really sure what the different types of buffers are (especially a "clock buffer") or how DCMs or DLLs work. If anyone could point me to some supplementary material that explains this stuff I'd really appreciate it. I suppose I'll need to also carefully comb over the datasheet for the DDR SDRAM since I'm feeling fairly fuzzy on how it works, too.

One thing I have noticed is that very few people seem to have my board. I guess it wasn't very popular. Also, the clock feedback pin for the SDRAM clock seemingly doesn't go into the right type of pin according to the manual -- it feeds into IO_L8N_GC_LC_3 (B7) but apparently only the P-sided inputs (eg IO_L8P_GC_LC_3) are appropriate for single-sided clocks. Though, again, I'm really not sure what I'm reading.

Thanks.

# ? Jul 20, 2010 04:59

SnoPuppy: Jun 15, 2005

Markov Chain Chomp posted:

So, I have http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,398,525&Prod=FX12 and it's been sitting around for a while. I recently found the Milkymist project and started using their cores and found some of the stuff works pretty well. Of course, I eventually decided to finally tackle the DDR SDRAM on my board using their core for it. I have to say that this failed spectacularly. I'm getting all sorts of timing issues because I have no idea what the hell I'm actually doing.

I realized that I need to slow down and actually read something that will help me understand what's even going on here to begin with. I'm a senior in a computer engineering program so a lot of signal and logic stuff has been very familiar, but all this clock stuff has me rather confused. I've been reading the Virtex 4 user manual trying to understand what the clocking resources do but unfortunately I'm coming up rather short. In particular, I'm not really sure what the different types of buffers are (especially a "clock buffer") or how DCMs or DLLs work. If anyone could point me to some supplementary material that explains this stuff I'd really appreciate it. I suppose I'll need to also carefully comb over the datasheet for the DDR SDRAM since I'm feeling fairly fuzzy on how it works, too.

One thing I have noticed is that very few people seem to have my board. I guess it wasn't very popular. Also, the clock feedback pin for the SDRAM clock seemingly doesn't go into the right type of pin according to the manual -- it feeds into IO_L8N_GC_LC_3 (B7) but apparently only the P-sided inputs (eg IO_L8P_GC_LC_3) are appropriate for single-sided clocks. Though, again, I'm really not sure what I'm reading.

Thanks.

I used that board in school too! Never used the DRAM on it though (but I have designed a DDR2 interface that used the Xilinx MIG, so I know my way around both.)

First, have you read the Virtex 4 users guide?
That should explain everything you need to know in much more detail than I will.

About the clocks.
Clocks that go into the FPGA have to be on clock capable pins, like a regional clock pin or a global clock pin (not always true, but generally so). Clocks that go out of the FPGA can use any pin. Global clocks can go anywhere on the FPGA using a dedicated global routing resource. Regional clocks are similar, but they are confined to a smaller region of the FPGA.

DCMs
The DCM allows clocks to be multiplied, divided and frequency shifted. It accomplishes this through the use of a DLL (delay locked loop) and frequency synthesizer.
The DLL is basically a phase comparator and a programmable delay chain. This allow the device to produce output clocks with a fixed relationship to the input clock.
Using the frequency synthesizer and the DLL, the DCM can function similar to a PLL

The MIG (Memory Interface Generator) is a relatively low level DRAM controller. It will program the memory and calibrate the capture routine, and then turn it over to the user (it also issues refresh cycles).
In order to correctly capture the data from the memory, it requires several clocks of specific frequency and phase relationship. These are required because the design assumes that it can safely move from one clock domain to another without the use of a FIFO.

How are you connecting the MIG? Do you have the appropriate clocks connected? What clock domain are the user output/inputs running on (On the designs I've used, they're on the DRAM clock domain)?

# ? Jul 20, 2010 15:38

blorpy: Jan 5, 2005

SnoPuppy posted:

I used that board in school too! Never used the DRAM on it though (but I have designed a DDR2 interface that used the Xilinx MIG, so I know my way around both.)

First, have you read the Virtex 4 users guide?
That should explain everything you need to know in much more detail than I will.

About the clocks.
Clocks that go into the FPGA have to be on clock capable pins, like a regional clock pin or a global clock pin (not always true, but generally so). Clocks that go out of the FPGA can use any pin. Global clocks can go anywhere on the FPGA using a dedicated global routing resource. Regional clocks are similar, but they are confined to a smaller region of the FPGA.

DCMs
The DCM allows clocks to be multiplied, divided and frequency shifted. It accomplishes this through the use of a DLL (delay locked loop) and frequency synthesizer.
The DLL is basically a phase comparator and a programmable delay chain. This allow the device to produce output clocks with a fixed relationship to the input clock.
Using the frequency synthesizer and the DLL, the DCM can function similar to a PLL

The MIG (Memory Interface Generator) is a relatively low level DRAM controller. It will program the memory and calibrate the capture routine, and then turn it over to the user (it also issues refresh cycles).
In order to correctly capture the data from the memory, it requires several clocks of specific frequency and phase relationship. These are required because the design assumes that it can safely move from one clock domain to another without the use of a FIFO.

How are you connecting the MIG? Do you have the appropriate clocks connected? What clock domain are the user output/inputs running on (On the designs I've used, they're on the DRAM clock domain)?

Thanks for the reply!

I have read the user manual but I feel like it assumes a bit more background on clocking issues that I've got, unfortunately.

I'm not using the MIG. I don't have access to the EDK or even the full ISE -- it's far too expensive and I'm not sure I can convince someone to give it to me for hobby purposes, even though I am a student. As a result, I'm using the milkymist cores. The milkymist SDRAM controller core does allow some calibration, but as far as I can tell, no amount of calibration will bring my timing within spec. I simply cannot get any given address to read the same thing twice.

Since you've actually used this board, do you happen to know if the SDRAM works at all? I know you said you haven't used it but maybe you know of someone who has? I'm fairly concerned about the pin setup that I mentioned. I'm getting a very major warning related to routing/clock buffers which I suspect is related to my problems with calibrating timing. Like I mentioned, the SDRAM clock feedback happens to be on the N-side of a global clock pin. According to the manual, for GC pins

quote:

These lower capacitance clock pins connect to Global Clock Buffers. These
pins do not support LVDS outputs, and they become regular user I/Os
when not needed for clocks. For single-ended clock inputs, use P-side pins
only.

which makes it seem like I'm SOL if the board is laid out wrong. The clock is most certainly single-ended yet it's connected to the N-side. The milkymist design needs that feedback clock and it seems like the synthesizer really wants it to be on a global clock, unfortunately.

Sorry, I feel like I rambled a little. Like I said, I have no idea what I'm talking about. Everyone tells me to read the Virtex 4 manual so I guess I'll read it yet again and hope something strikes me.

# ? Jul 20, 2010 16:18

Corrupt Politician: Aug 8, 2007

I used the Nexys2 board, which didn't have most of the features you're trying to use, so I can't really help you with the clock stuff. One of these days I'd love to pull it out of the closet and do something interesting with it.

Markov Chain Chomp posted:

I don't have access to the EDK or even the full ISE -- it's far too expensive and I'm not sure I can convince someone to give it to me for hobby purposes, even though I am a student. As a result, I'm using the milkymist cores. The milkymist SDRAM controller core does allow some calibration, but as far as I can tell, no amount of calibration will bring my timing within spec.

So Milkymist is a processor written in VHDL? Sounds pretty badass to me.

I've never used the full Xilinx ISE, what do you need to do that you can't do with the Webpack version?

# ? Jul 20, 2010 16:52

SnoPuppy: Jun 15, 2005

Markov Chain Chomp posted:

Thanks for the reply!

I have read the user manual but I feel like it assumes a bit more background on clocking issues that I've got, unfortunately.

I'm not using the MIG. I don't have access to the EDK or even the full ISE -- it's far too expensive and I'm not sure I can convince someone to give it to me for hobby purposes, even though I am a student. As a result, I'm using the milkymist cores. The milkymist SDRAM controller core does allow some calibration, but as far as I can tell, no amount of calibration will bring my timing within spec. I simply cannot get any given address to read the same thing twice.

Since you've actually used this board, do you happen to know if the SDRAM works at all? I know you said you haven't used it but maybe you know of someone who has? I'm fairly concerned about the pin setup that I mentioned. I'm getting a very major warning related to routing/clock buffers which I suspect is related to my problems with calibrating timing. Like I mentioned, the SDRAM clock feedback happens to be on the N-side of a global clock pin. According to the manual, for GC pins

which makes it seem like I'm SOL if the board is laid out wrong. The clock is most certainly single-ended yet it's connected to the N-side. The milkymist design needs that feedback clock and it seems like the synthesizer really wants it to be on a global clock, unfortunately.

Sorry, I feel like I rambled a little. Like I said, I have no idea what I'm talking about. Everyone tells me to read the Virtex 4 manual so I guess I'll read it yet again and hope something strikes me.

I've never used (or heard of) the milkymist cores, so I don't know anything about them. Are you sure the Xilinx MIG isn't in CoreGen? I haven't used the webpack in quite awhile, so I might be wrong, but I thought it was in there. You can instantiate the MIG in regular VHDL/Verilog - there's no need for the EDK. In fact, CoreGen will actually produce the raw source code so you can look at and examine it.

No idea what the "feedback" clock is, but that isn't a signal that comes from DRAM. The DRAM needs a clock, some control/address lines, and data/data strobe lines. I know that a DCM needs feedback, so that could be it.

edit:
After looking at the digilent reference manual, it appears that they externally feedback the DRAM clock to the FPGA. Is this the feedback you're referring to? How (or if) that is used will depend on the memory controller design.

edit2: Just looked at the milkymist DRAM controller. It's barely a DRAM controller (and even that's generous) - it doesn't look like it does much at all, and relies on software for the capture calibration and other very low level functions. All it does is give register access to the various DRAM control signals, and to the IODELAY elements on the FPGA pins.

SnoPuppy fucked around with this message at 02:19 on Jul 21, 2010

# ? Jul 20, 2010 20:35

blorpy: Jan 5, 2005

SnoPuppy posted:

I've never used (or heard of) the milkymist cores, so I don't know anything about them. Are you sure the Xilinx MIG isn't in CoreGen? I haven't used the webpack in quite awhile, so I might be wrong, but I thought it was in there. You can instantiate the MIG in regular VHDL/Verilog - there's no need for the EDK. In fact, CoreGen will actually produce the raw source code so you can look at and examine it.

No idea what the "feedback" clock is, but that isn't a signal that comes from DRAM. The DRAM needs a clock, some control/address lines, and data/data strobe lines. I know that a DCM needs feedback, so that could be it.

edit:
After looking at the digilent reference manual, it appears that they externally feedback the DRAM clock to the FPGA. Is this the feedback you're referring to? How (or if) that is used will depend on the memory controller design.

edit2: Just looked at the milkymist DRAM controller. It's barely a DRAM controller (and even that's generous) - it doesn't look like it does much at all, and relies on software for the capture calibration and other very low level functions. All it does is give register access to the various DRAM control signals, and to the IODELAY elements on the FPGA pins.

Oh, you're totally right about the MIG. Guh, I feel like such an idiot. Thanks for setting me straight. :shobon:

Also, yeah, I was referring to the externally routed signal that you mentioned. I was under the impression that it is needed in order to calibrate the controller correctly.

You're totally right about the milkymist controller. Since it's free and I know it works for them it seems like I could get it working, in theory, if I spent long enough with it. But it's much better if I just use the MIG and keep going with what I was doing.

Thanks so much!

# ? Jul 21, 2010 04:05

CapnBry: Jul 15, 2002; I got this goin'; Grimey Drawer

Here's something I thought I'd be able to figure out on my own but can't because I suck at electrons. I have this IRF510 MOSFET being driven by a 5v 500Hz PWM that I'm trying to use to control a 2.18W 12V DC fan.

I put a capacitor in there to stabilize the voltage and keep the fan from whining like my girlfriend. If I use a bigger value capacitor, the fan runs at ~12V most of the time, if I use anything lower, the whine gets louder.

So what I logically assumed is that when the gate opens, the fan pulls ~180mA and the unchecked current is filling the capacitor up which then stores enough power to keep the fan running at full speed even when the PWN is at like 70% duty. My dumb rear end figured the solution would be to put a low value resistor somewhere between the 12V and Ground to limit the current so the capacitor doesn't charge all the way up in the split second the gate is open. The question is, how many Ohms? If my math is right, a 66Ohm resistor would limit the current to 180ma so it would have to be less than that, but how much?

Am I going down the right path here?

# ? Jul 24, 2010 22:49

Mill Town: Apr 17, 2006

CapnBry posted:

Here's something I thought I'd be able to figure out on my own but can't because I suck at electrons. I have this IRF510 MOSFET being driven by a 5v 500Hz PWM that I'm trying to use to control a 2.18W 12V DC fan.

I put a capacitor in there to stabilize the voltage and keep the fan from whining like my girlfriend. If I use a bigger value capacitor, the fan runs at ~12V most of the time, if I use anything lower, the whine gets louder.

So what I logically assumed is that when the gate opens, the fan pulls ~180mA and the unchecked current is filling the capacitor up which then stores enough power to keep the fan running at full speed even when the PWN is at like 70% duty. My dumb rear end figured the solution would be to put a low value resistor somewhere between the 12V and Ground to limit the current so the capacitor doesn't charge all the way up in the split second the gate is open. The question is, how many Ohms? If my math is right, a 66Ohm resistor would limit the current to 180ma so it would have to be less than that, but how much?

Am I going down the right path here?

12V fans are generally brushless DC motors, and the whining and general weirdness is probably due to the interaction of the PWM with the brushless fan's own internal controller chip rather than anything to do with the capacitor.

You need to find a fan that accepts PWM input to its controller and get rid of the MOSFET, or use the current setup with a brushed DC motor.

# ? Jul 24, 2010 23:19

BattleMaster: Aug 14, 2000

I've got some 12V, 1.3Ah sealed lead-acid batteries that need charging. Is it safe to use a variable bench power supply to charge them?

# ? Jul 25, 2010 22:18

catbread.jpg: Feb 22, 2007

If it's a current-limited type, sure.

Find out the required charge voltage and current and go nuts.

# ? Jul 26, 2010 06:15

BattleMaster: Aug 14, 2000

Cool, thanks. All the specs are listed on the battery casing so I should be good to go. I actually don't own a suitable power supply yet but was planning on going out today to shop for one.

# ? Jul 26, 2010 17:02

Corrupt Politician: Aug 8, 2007

Can anyone here help me with driving power mosfets at high voltages and RF frequencies? I'm trying to take the advice you guys gave me earlier of using an H-bridge instead of that obsolete op amp, and I want to drive the transistors at variable PWM with a microcontroller or some type of digital logic. The mosfets need something on the order of 3A of current on the gate to switch fast enough. The gate will also need to be a really high voltage (160V) relative to ground in order to have Vgs equal to 10V, since the source voltage will be at 170V. Obviously I don't have a function generator that can supply that kind of voltage and current. I've been trying to give myself a crash course in power electronics over the past few weeks, but I'm confused about this.

If I described it poorly, let me know and I'll draw a picture.

# ? Jul 27, 2010 20:55

insta: Jan 28, 2009

Corrupt Politician posted:

Can anyone here help me with driving power mosfets at high voltages and RF frequencies? I'm trying to take the advice you guys gave me earlier of using an H-bridge instead of that obsolete op amp, and I want to drive the transistors at variable PWM with a microcontroller or some type of digital logic. The mosfets need something on the order of 3A of current on the gate to switch fast enough. The gate will also need to be a really high voltage (160V) relative to ground in order to have Vgs equal to 10V, since the source voltage will be at 170V. Obviously I don't have a function generator that can supply that kind of voltage and current. I've been trying to give myself a crash course in power electronics over the past few weeks, but I'm confused about this.

If I described it poorly, let me know and I'll draw a picture.

You might have source and drain backwards. Source on a MOSFET is the (-) terminal, whereas drain is the (+) one. You need 10V into the gate relative to ground to control 170V. If you're using a double-ended supply with +170 and -170V, you will need N and P channel MOSFETs. If you're trying to generate a 370V P-P signal from a 170V supply, then an H-bridge will do what you want. Definitely look into pre-packaged MOSFET drivers, as they're already equipped to translate a logic 0/1 into proper gate-slamming.

# ? Jul 27, 2010 21:23

Corrupt Politician: Aug 8, 2007

insta posted:

You need 10V into the gate relative to ground to control 170V.

The source isn't tied to the ground, it's going to be varying between +170V and -170V.

quote:

If you're using a double-ended supply with +170 and -170V, you will need N and P channel MOSFETs.

This is what I'm trying to do. Basically a class AB output. I have the N and P channel MOSFETs, I just don't know how to switch them rapidly.

quote:

Definitely look into pre-packaged MOSFET drivers, as they're already equipped to translate a logic 0/1 into proper gate-slamming.

Digikey doesn't seem to have any that can switch fast enough. I'd like to have a total switching time of less than 100ns, and the delay on the MOSFET drivers seems to be a good bit more than that.

# ? Jul 27, 2010 22:10

catbread.jpg: Feb 22, 2007

Delay doesn't imply switching time though. You'll get better efficiency will all N-type devices. You'll need gate drivers in any case. Why do you mention class AB? You want to be using the switches fully on/off. What was the bandwidth you needed again?

# ? Jul 28, 2010 07:57

ANIME AKBAR: Jan 25, 2007; afu~

Corrupt Politician posted:

Can anyone here help me with driving power mosfets at high voltages and RF frequencies? I'm trying to take the advice you guys gave me earlier of using an H-bridge instead of that obsolete op amp, and I want to drive the transistors at variable PWM with a microcontroller or some type of digital logic. The mosfets need something on the order of 3A of current on the gate to switch fast enough. The gate will also need to be a really high voltage (160V) relative to ground in order to have Vgs equal to 10V, since the source voltage will be at 170V. Obviously I don't have a function generator that can supply that kind of voltage and current. I've been trying to give myself a crash course in power electronics over the past few weeks, but I'm confused about this.

If I described it poorly, let me know and I'll draw a picture.

specialty ICs are made specifically for driving high-side N-channel mosfets for half or full bridge configurations. They're called bootstrapping gate drivers, and they allow you to drive the gates of your high side switch to very high voltages, while the driver itself only requires 10V or so. I've used the FAN73711 before with good results. You can also get chips that handle both high and low side mosfets at the same time, so you would only need two for the entire bridge. The FAN7390 is such a device.

Corrupt Politician posted:

Digikey doesn't seem to have any that can switch fast enough. I'd like to have a total switching time of less than 100ns, and the delay on the MOSFET drivers seems to be a good bit more than that.

Wait, are you trying to synthesize a sine wave via pwm? That seems unnecessary... and even so, 100ns switching times is probably faster than you need, especially if you filter your output.

ANIME AKBAR fucked around with this message at 10:16 on Jul 28, 2010

# ? Jul 28, 2010 10:14

Corrupt Politician: Aug 8, 2007

catbread.jpg posted:

Delay doesn't imply switching time though. You'll get better efficiency will all N-type devices. You'll need gate drivers in any case. Why do you mention class AB? You want to be using the switches fully on/off. What was the bandwidth you needed again?

I was under the impression that the delay on a gate driver was added to the total switching time (driver delay + MOSFET rise time = total), is that not the case? Does it switch just as fast, just phase shifted by the delay time? I need to produce a 500KHz square wave so the absolute maximum switch time would be 1us for 50% duty cycle, but I want to be able to vary the duty cycle down to maybe 5-10%, so I'd need faster than that.

The class AB part was probably incorrect wording. As you can see I don't know too much about power electronics, or analog in general beyond the basic behavior of transistors, diodes and op amps. I've been trying to fill in some gaps over this summer for classes I didn't have time to take.

ANIME AKBAR posted:

specialty ICs are made specifically for driving high-side N-channel mosfets for half or full bridge configurations. They're called bootstrapping gate drivers, and they allow you to drive the gates of your high side switch to very high voltages, while the driver itself only requires 10V or so. I've used the FAN73711 before with good results. You can also get chips that handle both high and low side mosfets at the same time, so you would only need two for the entire bridge. The FAN7390 is such a device.

I was just looking at similar ICs on Digikey and wondering if they are for what I am trying to do. Glad to know I'm on the right track. It's pretty cool when I'm having trouble with a circuit and then find out there is a component designed to solve my exact problem.

quote:

Wait, are you trying to synthesize a sine wave via pwm? That seems unnecessary... and even so, 100ns switching times is probably faster than you need, especially if you filter your output.

I'm not trying to synthesize a sine wave, I ultimately want to use pwm to control the power output. 10% duty cycle at 500KHz would mean I'd need a switching time of 200us maximum. And wouldn't I want it lower than the absolute maximum, just so I don't have huge switching losses?

# ? Jul 28, 2010 15:36

ANIME AKBAR: Jan 25, 2007; afu~

Corrupt Politician posted:

I was under the impression that the delay on a gate driver was added to the total switching time (driver delay + MOSFET rise time = total), is that not the case? Does it switch just as fast, just phase shifted by the delay time? I need to produce a 500KHz square wave so the absolute maximum switch time would be 1us for 50% duty cycle, but I want to be able to vary the duty cycle down to maybe 5-10%, so I'd need faster than that.

The class AB part was probably incorrect wording. As you can see I don't know too much about power electronics, or analog in general beyond the basic behavior of transistors, diodes and op amps. I've been trying to fill in some gaps over this summer for classes I didn't have time to take.

I was just looking at similar ICs on Digikey and wondering if they are for what I am trying to do. Glad to know I'm on the right track. It's pretty cool when I'm having trouble with a circuit and then find out there is a component designed to solve my exact problem.

I'm not trying to synthesize a sine wave, I ultimately want to use pwm to control the power output. 10% duty cycle at 500KHz would mean I'd need a switching time of 200us maximum. And wouldn't I want it lower than the absolute maximum, just so I don't have huge switching losses?

Okay, lets nail down a few things. What do you want your output stage to be like? Do you want your output to have a DC offset, or be AC only (you keep saying square wave, but that is sort of vague)? You keep mentioning duty cycle, but duty cycle control is only useful to produce an average DC signal. If that doesn't make sense, then think of it like this; the power you deliver to your load is going to be proportional to the RMS voltage you apply to it (assuming the load is resistive). Now, consider a square wave whose voltage switches between 0V and 100V. The RMS value of this voltage is going to be proportional to your duty cycle. Now consider a square wave whose voltage switches between -100 and +100. The duty cycle of this waveform has no effect on its rms voltage, and thus will not change the average power it delivers.

The first waveform can be easily made with just a half bridge circuit. The second waveform can be done with a complementary full bridge. I would suggest you get two half bridges which can be independently controlled. There are a lot of ways I can think of that would allow you to control average delivered power, and such a setup would allow you to use most of them (although you may need a slightly more sophistocated method of generating the signals to your drivers).

If you're unclear on all the full bridge/half bridge and waveform stuff, I can take a step back and explain more in detail.

# ? Jul 28, 2010 19:05

Zo: Feb 22, 2005; LIKE A FOX

Yeah and to add, if you DO want to control the power but still switch between +170/-170V or whatever, the approach of choice is phase-shift PWM control which is a lot more efficient than amplitude control (horribly inefficient). This would start to get complicated and a DSP would be your best solution.

Actually, I sat in on a siemens talk at a trade show last week and they had an interesting way to do this, the bart simpson modulation technique: gate at the frequency you want normally to generate a standard AC square wave, then PWM one of the two gates (for each pair) at a 20 times higher frequency. This will generate a waveform that looks like alternating bart heads at varying amplitude (depending on the duty cycle of the higher frequency PWM).

# ? Jul 28, 2010 19:22

catbread.jpg: Feb 22, 2007

Who was it here who posted about ultrasonic sonar? I'm keen to chat.

# ? Jul 30, 2010 02:34

ANIME AKBAR: Jan 25, 2007; afu~

catbread.jpg posted:

Who was it here who posted about ultrasonic sonar? I'm keen to chat.

pretty sure you're talking about the continuous signal SODAR I posted about in fall 2008. What's up?

# ? Jul 30, 2010 13:50

catbread.jpg: Feb 22, 2007

ANIME AKBAR posted:

pretty sure you're talking about the continuous signal SODAR I posted about in fall 2008. What's up?

I'm doing a DSP course, and the main component is a project. We have Spectrum Digital dev boards with a TMS320C5510 and an AIC23 96 kHz audio codec amongst other things.

I've been looking at the feasibility of doing 40 kHz SONAR, some back of the envelope calculations tell me that at least the chip is more than capable (200 MHz/400 MMACs).

What I want to do is continuous operation based on a precomputed output sequence, constantly filling an input buffer and then performing correlation-based TOF recovery on a fast-as-it-can basis. 1K samples gets 2m of range (just an initial working target), but I was planning on using a sequence length of something like 8K to provide a longer unambiguous range. That should theoretically provide up to 400 1K*1K (I realise that the choice of correlation length does not necessarily have to be the same as the depth of the shift but it's handy enough for now) point correlations per second (ignoring overhead), so effectively real time and probably faster than I can dump and display the data.

As far as feasibility goes, I'm now looking at whether the 96 kHz audio codec will be enough. I think 40 kHz transducers with 1 kHz bandwidth are readily available, so I'm looking at BPSK sequences. Fortunately, this project doesn't have to demonstrate amazing ranging performance, I'm concentrating more on the elegance of the implementation on the DSP architecture, hence the continuous operation and gratuitous use of buffering. I've looked at the analogue front end and fortunately there's no audio-band LPF, but I'll have to do more calculations to see about that sampling frequency.

# ? Jul 31, 2010 00:43

catbread.jpg: Feb 22, 2007

So yeah, any tips/glaring oversights at this stage?

# ? Jul 31, 2010 00:44

ANIME AKBAR: Jan 25, 2007; afu~

For our platform we had a cyclone III FPGA as the platform. The DSP guy in our group developed a cross correlation architecture that allowed it to do full cross correlations at 200KHz. In the end, the fpga was doing about 2,500 MMACs, and the raw correlation had a bandwidth of something like 40 gigabits/s. That is while running a couple FIR filters and the serial interfaces for our ADC and DAC. I don't think a TMS320 has the capacity to do the same thing.

Now, I was saying over the course of the project that doing the correlation so fast, while amazing, didn't make any drat sense and would only make it hard for us to export the data (in the end we really couldn't). There really wasn't any reason to do it like that other than the fact that is was flashy. There's probably no reason you can't implement the same general idea with your hardware, except that you'll have to use a completely different, and much slower, correlation architecture.

For our transmit sequence we simply used a LFSR whose output was run through a FIR bandpass filter to produce bandlimited noise. What's you're reasoning behind wanting to do BPSK? And having just 1KHz of bandwidth is likely going to cripple your distance resolution. We used these transducers, which have great bandwidth (but were very directional, which may be good or bad depending on your application).

I don't really know anything about audio codecs except everyone I know who has tried to interface with them has said they're a pain in the rear end. If possible I'd try to keep things simple and go with a DAC and ADC.

# ? Jul 31, 2010 03:59

SnoPuppy: Jun 15, 2005

1 kHz of bandwidth is really going to hurt. The range resolution for a chirp will be equal to the velocity of propagation divided by 2*the bandwidth, and I want to say that this is the theoretical max for any band limited signal (including coded chips).

You're using pizeo transducers, aren't you? These have the issue of having an extremely high q, so they ring pretty badly and tend to make coded chips almost worthless.

Now, there's nothing that says you have to use ultrasound, is there? You could actually send it in the audio spectrum, where you could get reasonable microphones/speakers that cover a wider bandwith. Plus you get to make annoying noises!

I'd also suggest looking into using a linear fm chirp instead-all you have to do is mix the recieving chirp with the transmitting chirp and you will produce single tones that are proportional to the echo distance. Take an FFT and you're pretty much done.

# ? Jul 31, 2010 07:20

catbread.jpg: Feb 22, 2007

I haven't got close to selecting a sensor (my ignorance in the subject area should be obvious), but that one that you linked looks good. It seems that you have to go for electrostatics to get reasonable bandwidth, was there any difficulties with the high voltage amplifier? What about the receiver?

Bandlimited noise is certainly one way to go, I want to use a precomputed sequence (which of course can be precomputed bandlimited noise) for architectural reasons which opens up the possibility of using sequences designed for better correlation properties.

I'm not too worried about the codec, there are existing drivers which do a great job of shovelling data in and out of memory. I'm also not worried about the computing power, it seems that both of our projects are overkill in that regard.

My goal for the project at this stage is to demonstrate reasonably accurate ranging with an update rate which is as fast as can be achieved, with architectural niceness as a priority, which is why chirp-based approaches aren't as appealing, though I would use them if necessary (it does seem to be the way to get the best ranging performance out of a low-bandwidth transducer).

# ? Jul 31, 2010 10:26

SnoPuppy: Jun 15, 2005

catbread.jpg posted:

I haven't got close to selecting a sensor (my ignorance in the subject area should be obvious), but that one that you linked looks good. It seems that you have to go for electrostatics to get reasonable bandwidth, was there any difficulties with the high voltage amplifier? What about the receiver?

Bandlimited noise is certainly one way to go, I want to use a precomputed sequence (which of course can be precomputed bandlimited noise) for architectural reasons which opens up the possibility of using sequences designed for better correlation properties.

I'm not too worried about the codec, there are existing drivers which do a great job of shovelling data in and out of memory. I'm also not worried about the computing power, it seems that both of our projects are overkill in that regard.

My goal for the project at this stage is to demonstrate reasonably accurate ranging with an update rate which is as fast as can be achieved, with architectural niceness as a priority, which is why chirp-based approaches aren't as appealing, though I would use them if necessary (it does seem to be the way to get the best ranging performance out of a low-bandwidth transducer).

You could get two transmitters and do electronic beam steering by phasing them.
Band limited white noise is nice because it has very good auto correlation properties-your other choice is a Barker code, but the longest known one is only 13 bits.

The problem a chip coded pulse has is that any target velocity introduces a Doppler shift in the echo and messes up the correlation. Continuous wave FM chirps are nice because they still work if your target is moving. This may not matter in your application though.

Of course, an entirely different cool thing would be to just build your own radar!, With eBay you could do it for a few hundred...
Check out this page:
http://www.mit.edu/~gr20603/Dr.%20Gregory%20L.%20Charvat%20Projects/$240%20High%20Res%20Rail%20SAR.html

# ? Jul 31, 2010 12:13

Cyril Sneer: Aug 8, 2004; Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Not sure if anyone would know the answer to this but I'll ask anyway. I guess my next stop would be the fine folks over at pupman.com

Lets say we have a nice, single-shot DC electric discharge. This produces a broadband response in the frequency domain. What happens as we increase the discharge frequncy? From say, once per minute, to once per second, to kilohertz, to megahertz? Basically, what is the frequency content of a, say, 100 MHz electric discharge (at say 1 Hz, each pulse stands alone and produces a wideband frequency response, but what happens as that time-frequency increases and one event "blurs" into the next [a kind of intersymbol interference])?

Along a similar line, is there a difference, frequency-spectrum-wise, between a spark and an arc (an arc being a continuous sustained plasma channel)? And how does oscillation frequency factor in?

# ? Jul 31, 2010 21:25

ANIME AKBAR: Jan 25, 2007; afu~

catbread.jpg posted:

I haven't got close to selecting a sensor (my ignorance in the subject area should be obvious), but that one that you linked looks good. It seems that you have to go for electrostatics to get reasonable bandwidth, was there any difficulties with the high voltage amplifier? What about the receiver?

We generated the drive signal with power op amps and a custom step up transformer. Also keep in mind that in order for electrostatic transducers to work, you need to bias them with DC (like 150V for this one). At first we were planning to make this bias voltage with a boost converter, but we found that with a simple diode/capacitor circuit we could have the thing self-bias.

quote:

Bandlimited noise is certainly one way to go, I want to use a precomputed sequence (which of course can be precomputed bandlimited noise) for architectural reasons which opens up the possibility of using sequences designed for better correlation properties.

I was under the impression that, by definition, white noise has the best correlation properties (its autocorrelation function is simply an impulse).

# ? Aug 1, 2010 04:46

SnoPuppy: Jun 15, 2005

ANIME AKBAR posted:

I was under the impression that, by definition, white noise has the best correlation properties (its autocorrelation function is simply an impulse).

You're sort of correct. Band limited noise isn't the same as true white noise, so for a fixed length random sequence, some will be better than others.

# ? Aug 1, 2010 05:29

murphle: Mar 4, 2004

I have a basic question about de-soldering parts. I'm trying to remove some through-hole components from a pcb using my adjustable Weller iron and some desoldering braid. Every once in a while the braid will work wonderfully and wick up all the solder on the pad I'm working. But most of the time I just sit there with the tip pressing on the braid pressing on the solder, and the solder won't wick. The solder is melting, but not wicking. Is the braid dirty, or in need of extra prep, or what? The braid looks clean and shiny. Should I be putting some flux on stuff, or maybe cleaning flux off of stuff? These are all pads that I originally soldered myself using some rosin-core leaded solder.

# ? Aug 3, 2010 03:01

Zo: Feb 22, 2005; LIKE A FOX

murphle posted:

I have a basic question about de-soldering parts. I'm trying to remove some through-hole components from a pcb using my adjustable Weller iron and some desoldering braid. Every once in a while the braid will work wonderfully and wick up all the solder on the pad I'm working. But most of the time I just sit there with the tip pressing on the braid pressing on the solder, and the solder won't wick. The solder is melting, but not wicking. Is the braid dirty, or in need of extra prep, or what? The braid looks clean and shiny. Should I be putting some flux on stuff, or maybe cleaning flux off of stuff? These are all pads that I originally soldered myself using some rosin-core leaded solder.

You mean wick right?

1. Put wick directly over solder you wish to remove
2. Put iron on top of wick
3. Add a small bit of solder on to the wick to get it started

# ? Aug 3, 2010 03:53

ANIME AKBAR: Jan 25, 2007; afu~

In the past I've bought copper braid that was completely worthless because it didn't have any rosin on it. It's pretty difficult to tell by looking, so that may be your problem. Also keep in mind that it will never get all the solder off the pads. There will always be some left behind, and that's what makes desoldering through-hole parts so difficult.

# ? Aug 3, 2010 04:00

murphle: Mar 4, 2004

Thanks for the suggestions. There's no guarantee that my braid has any rosin on it. I think my current roll is from Radio Shack, so it may be complete garbage. I haven't been putting any solder on the braid to help get it started, so I'll try that next time.

# ? Aug 3, 2010 05:22

therunningman: Jun 28, 2005; ...'e 'ad to spleet.

I am making a small noise making circuit using a few op-amps. I want to able to switch between a square and a triangle waves at different audio frequencies I can then mix together. Real lo-fi stuff.

I want to be able to run it from a battery or a simple wall wart so I am using an op-amp to make a virtual ground for the wave generating part of the circuit.
I get nice square and triangle waves using two TL081, but the square wave is much louder than the triangle.
I tried to add a non-inverting amplifier to the triangle wave using another TL081, but it starts to flatten the valleys of the triangle wave before I can amplify it enough.

Why is this happening? Is this a completely wrong way of going about it? It is hacked together from snippets of datasheets. I am slowly picking this stuff up through osmosis so any help is greatly appreciated.

# ? Aug 3, 2010 17:43

Corla Plankun: May 8, 2007; improve the lives of everyone

therunningman posted:

I am making a small noise making circuit using a few op-amps. I want to able to switch between a square and a triangle waves at different audio frequencies I can then mix together. Real lo-fi stuff.

I want to be able to run it from a battery or a simple wall wart so I am using an op-amp to make a virtual ground for the wave generating part of the circuit.
I get nice square and triangle waves using two TL081, but the square wave is much louder than the triangle.
I tried to add a non-inverting amplifier to the triangle wave using another TL081, but it starts to flatten the valleys of the triangle wave before I can amplify it enough.

Why is this happening? Is this a completely wrong way of going about it? It is hacked together from snippets of datasheets. I am slowly picking this stuff up through osmosis so any help is greatly appreciated.

You should probably quiet the square-wave instead of amplifying the triangle one. Once those two are playing nicely together you could amplify the whole mess with a proper power amplifier.

The flat tops on your triangles are probably caused by trying to make the amplifier supply more voltage than you are giving it in the first place. Its output is "saturating".

Square waves are also just easier to hear in the first place. Triangle waves are almost as subtle as sine waves.

# ? Aug 3, 2010 18:14

Corla Plankun: May 8, 2007; improve the lives of everyone

On a completely unrelated note, I am trying to teach myself VHDL this summer because I didn't really "get" it when I took digital systems last semester. I'm using Circuit Design with VHDL by Pedroni and it has mentioned a lot of things (For example: d'VAL(pos), d'POS(value), d'LEFTOF(value) and d'VAL(row, column); and Rem, Mod and Abs) that there is "little or no synthesis support" for.

What exactly does this mean? I am guessing it means I can write and program devices with them, but I can't test them. I don't NEED to use them or anything, so I'm fine with just avoiding them for now, but I keep running in to the "little or no support" warning in this book and it'd be nice to understand it.

# ? Aug 3, 2010 18:23

therunningman: Jun 28, 2005; ...'e 'ad to spleet.

Thanks, that is a good point to bring the square down instead. I'll look into that.

It is the valleys of the triangle wave that gets clipped and not the tops. Is it because of the virtual ground I am using?

# ? Aug 3, 2010 18:48

Adbot: ADBOT LOVES YOU

# ? Jun 3, 2024 17:04

SnoPuppy: Jun 15, 2005

Corla Plankun posted:

On a completely unrelated note, I am trying to teach myself VHDL this summer because I didn't really "get" it when I took digital systems last semester. I'm using Circuit Design with VHDL by Pedroni and it has mentioned a lot of things (For example: d'VAL(pos), d'POS(value), d'LEFTOF(value) and d'VAL(row, column); and Rem, Mod and Abs) that there is "little or no synthesis support" for.

What exactly does this mean? I am guessing it means I can write and program devices with them, but I can't test them. I don't NEED to use them or anything, so I'm fine with just avoiding them for now, but I keep running in to the "little or no support" warning in this book and it'd be nice to understand it.

The synthesizer is what turns your vhdl into gates and flip-flops. Certain aspects of vhdl cannot be cleanly synthesized because they too difficult to represent in logic. You won't be able to compile a design and run it on real hardware if your synthesizer doesn't support the operations, but you can still simulate using them.

# ? Aug 3, 2010 18:51

The Something Awful Forums > Discussion > Hobbies, Crafts, & Houses > Learning electronics: Release the Magic Blue Smoke

«‹›782 »