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Kazinsal
Dec 13, 2011


movax posted:

Uhhhhh, "license-based downclocking", is that what I think it is?

Also whatever Zen2 supports is what AAA / "big" games are going to assume for the next...5 years, I guess?

If Intel takes a page from Cisco and charges successively higher orders of magnitude to make your maximum oomph go up I'll poo poo a brick

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Paul MaudDib
May 3, 2006

TEAM NVIDIA:
FORUM POLICE

movax posted:

Uhhhhh, "license-based downclocking", is that what I think it is?

Also whatever Zen2 supports is what AAA / "big" games are going to assume for the next...5 years, I guess?

"license-based downclocking" is how Intel refers to the clock regimes of AVX-based downclocking. When the chip has pumped up the voltage enough to run AVX properly, the processor "has a license to run in L1 state" or whatever.

https://stackoverflow.com/questions/56852812/simd-instructions-lowering-cpu-frequency/56861355#56861355

Of course power/thermal/current limits will always exist (unless the motherboard removes them) but license-based downclocking is what is responsible for AVX performance regressions in mixed workloads. Ice Lake basically gets rid of that and will be able to handle AVX-512 in mixed workloads just fine, it's when you're doing poo poo like Prime95 that is just hammering the AVX that the electrical/thermal limits that electrical/thermal will come into play.

Cloudflare's entire crypto task (of which not all is AVX-512) was 2.5% of the total load so that's not something that is going to run the chip into electrical/thermal limiting. That's the prototypical example of "mixed workload that produces a performance regression" and it will do fine on Ice Lake.

If you are running code that is not so mixed and uses a whole bunch of AVX instructions... it is actually increasing your efficiency. Efficiency is "work / power". Yes, it uses somewhat more power at any one instant, but you get a bigger increase in throughput than you get an increase in power.

The tradeoff is of course that AVX takes up a decent chunk of die space (and again, I think it is probably a better idea to go with 256-bit width and emulate 512b in two instructions). But in performance terms, as long as license-based downclocking is not loving you up in mixed workloads, there's no reason not to have it for the workloads it does help. Nobody serious actually thinks we should go back to a world without SIMD acceleration, that would suck, even ARM has moved in that direction with NEON and SVE.

Paul MaudDib fucked around with this message at 06:54 on Jan 3, 2021

trilobite terror
Oct 20, 2007
BUT MY LIVELIHOOD DEPENDS ON THE FORUMS!

Arivia posted:

2021 is the year of linux on the arm desktop

:smug: I’ve been surfing the forums on a Rpi4 running Ubuntu since May

BurritoJustice
Oct 9, 2012


License based downclocking is much more insidious if you're tinkering at a deeper level with maxed out cooling/limits because it is its own thing that overrides what you typically set while overclocking. It's a good reason why a lot of basic reddit-level overclocks barely ever run at rated because they don't touch any of the AVX offsets and they are increasingly common workloads nowadays.

If you can't get around it like you can with unlockable chips, it's a pretty big performance cut.

repiv
Aug 13, 2009

Paul MaudDib posted:

Nobody serious actually thinks we should go back to a world without SIMD acceleration, that would suck, even ARM has moved in that direction with NEON and SVE.

SVE is pretty cool, it feels like Intel missed a trick by not going in that direction. They decoupled the instruction set from the vector width so you can have one code path that targets anything from 128-bit to 2048-bit hardware.

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

repiv posted:

SVE is pretty cool, it feels like Intel missed a trick by not going in that direction. They decoupled the instruction set from the vector width so you can have one code path that targets anything from 128-bit to 2048-bit hardware.

It's cool maybe, in theory. It's an optional feature rather than core ISA, and despite being several years old now, almost nobody's using it. The only core with SVE I'm aware of is Fujitsu's supercomputer ARM core.

Everyone else seems happy to stick with NEON. Notably, M1 doesn't support SVE. It provides SIMD throughput equivalent to a 512-bit vector unit by throwing in four 128-bit NEON units. That approach wouldn't be practical without M1's 8-wide decode and dispatch, but if you've got that and an insane reorder window, why not?

repiv
Aug 13, 2009

ARM is obviously putting SVE in their reference server cores, which Amazon use as the basis for their Graviton processors, so it'll probably show up on AWS at some point

It's early days though, yeah

ColTim
Oct 29, 2011

Paul MaudDib posted:

The tradeoff is of course that AVX takes up a decent chunk of die space (and again, I think it is probably a better idea to go with 256-bit width and emulate 512b in two instructions).

For some context, this has a comparison of the client vs. server skylake cores.

ColTim fucked around with this message at 04:00 on Jan 4, 2021

gradenko_2000
Oct 5, 2010

HELL SERPENT
Lipstick Apathy
https://twitter.com/ComputerBase/status/1346375123402698752

Intel is discontinuing Z390, Z370, H370, H310C, H310D, B360, B365, and (mobile) QMS380 chipsets. Production will continue until July 2021, and then the last deliveries will run until the beginning of 2022.

This is congruent with 9th gen CPUs already getting their discontinuation announcement last year.

We expect that we'll hear about the 500-series chipset during CES 2021 on January 11th, which should coincide with them supporting Rocket Lake (rumored for a release in March).

SwissArmyDruid
Feb 14, 2014

by sebmojo

Arivia posted:

2021 is the year of linux on the arm desktop

We are actually so goddamn close. All I need is some SR-IOV or GVT-g support on a consumer graphics card and I will never look back at Windows as a desktop operating system, only ever in VMs.

SwissArmyDruid fucked around with this message at 17:37 on Jan 5, 2021

repiv
Aug 13, 2009

Paul MaudDib posted:

"license-based downclocking" is how Intel refers to the clock regimes of AVX-based downclocking. When the chip has pumped up the voltage enough to run AVX properly, the processor "has a license to run in L1 state" or whatever.

I've just been reading up on the quirks of the license system and learned that speculative execution can trigger it :whitewater:

If you're writing a library and want to avoid messing with the power state you might be tempted to do something like

code:
if cpu_has_256bit_penalty() {
    do_128bit_path();
} else {
    do_256bit_path();
}
...but branch mispredictions will randomly cause the CPU to downclock even though the 256bit branch never actually gets taken

gross

DrDork
Dec 29, 2003
commanding officer of the Army of Dorkness

repiv posted:

...but branch mispredictions will randomly cause the CPU to downclock even though the 256bit branch never actually gets taken

I have to say that avoiding non-deterministic behavior like that is one of the blessings I never expected to reap by not going into such low-level development work as a career.

BlankSystemDaemon
Mar 13, 2009



repiv posted:

code:
if cpu_has_256bit_penalty() {
    do_128bit_path();
} else {
    do_256bit_path();
}
...but branch mispredictions will randomly cause the CPU to downclock even though the 256bit branch never actually gets taken

gross
I love computers. :allears:

Indiana_Krom
Jun 18, 2007
Net Slacker

repiv posted:

I've just been reading up on the quirks of the license system and learned that speculative execution can trigger it :whitewater:

If you're writing a library and want to avoid messing with the power state you might be tempted to do something like

code:
if cpu_has_256bit_penalty() {
    do_128bit_path();
} else {
    do_256bit_path();
}
...but branch mispredictions will randomly cause the CPU to downclock even though the 256bit branch never actually gets taken

gross

Speculative/out of order execution for the win. (Modern CPUs may execute both possible branches ahead of time and then discard whichever one is determined to be invalid when the actual branch is decided.)

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

Indiana_Krom posted:

Speculative/out of order execution for the win. (Modern CPUs may execute both possible branches ahead of time and then discard whichever one is determined to be invalid when the actual branch is decided.)

I don't think many modern CPU architectures actually do that. It's an idea that's been kicking around for a while, but has generally proven to be too inefficient to actually use.

Basically, you're guaranteed to waste half the energy spent executing instructions after the branch prior to branch resolution. You also take a SMT-style performance penalty on both sides. Since energy efficiency and performance are closely tied together these days, it's generally better to invest in a good branch predictor and gamble that you choose the correct path most of the time. The proportion of energy spent on incorrect code paths is lower as long as your predictor's good.

BlankSystemDaemon
Mar 13, 2009



BobHoward posted:

I don't think many modern CPU architectures actually do that. It's an idea that's been kicking around for a while, but has generally proven to be too inefficient to actually use.

Basically, you're guaranteed to waste half the energy spent executing instructions after the branch prior to branch resolution. You also take a SMT-style performance penalty on both sides. Since energy efficiency and performance are closely tied together these days, it's generally better to invest in a good branch predictor and gamble that you choose the correct path most of the time. The proportion of energy spent on incorrect code paths is lower as long as your predictor's good.
It's used in Neoverse, the fastest ARM IP core to date, and it also exists in the RISC-V E51 and the E54, and it's also used in the RISC-V BOOM processor, as well as POWER9.
Admittedly, some of those implementations (probably) aren't as advanced as the ones in Intel or AMD processors, but they're still used.

BlankSystemDaemon fucked around with this message at 10:44 on Jan 6, 2021

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull
^^ not sure you understood the post I was responding to?

Indiana_krom was talking about an alternative to speculative execution that was once thought to have promise. It's the brute force approach: don't bother predicting branches, just execute both sides of the branch. In practice, that might look something like a SMT CPU which normally runs only one thread, but automatically starts a second every time it encounters a branch. One thread follows the branch-taken path, the other the not-taken, and once the branch resolves the thread for the wrong side of the branch is thrown away.

The advantage of this concept is that you never guess wrong. The core is always making real forward progress on the program. It will never have to backtrack. Half of that progress is wrong, but if the execution resources are wide enough, the two sides of the branch might even perform close to as fast as they would if they were the only thing running.

In the world where Dennard scaling didn't get murdered in the mid-oughts we might have seen this idea gain acceptance outside academic papers. But in the real world, the power and area penalty has prevented it from being used much (at all?) in commercial products.

ColTim
Oct 29, 2011
I thought part of the software spectre fix was to insert hacky code to prevent speculative execution on certain branches (c.f. here).

BlankSystemDaemon
Mar 13, 2009



ColTim posted:

I thought part of the software spectre fix was to insert hacky code to prevent speculative execution on certain branches (c.f. here).
Yeah, and that in and of itself proves how broad speculative execution is, because one or more variants of meltre existed on all architectures I know of, including SPARC64.

Beef
Jul 26, 2004
The CPU will speculate which branch will be taken, determined by the branch predictor on historical data (or compiler hints, a untaken assert is virtually free). It will not compute both branches at the same time, at least not in the backends I've worked with. I think GPUs do that in a certain way to handle divergent warps.

The vast majority of branches are correctly predicted. Mispredicts happen mostly in situations where the branch depends on dynamic data, such as a sorting routine or string search. A 100% taken/untaken branch is basically for free. If the branch predictor is not seeing a trend (something like 90 or 80% threshold) it will not cause speculation.
You can test this yourself, worst case are the 80/20 or 70/30 cases because it will sometimes trick the predictor with a sequence above the threshold and then cause mispredicts.

In short, that 128/256 avx throttling due to mispredict is not something you will get in the wild, unless you are doing some really weird shots.

shrike82
Jun 11, 2005

lol I didn’t realize Jim Keller rejoined Intel and left again purportedly due to an internal argument about outsourcing.

WhyteRyce
Dec 30, 2001

shrike82 posted:

lol I didn’t realize Jim Keller rejoined Intel and left again purportedly due to an internal argument about outsourcing.

Never heard it was over an outsourcing argument but Intel does love trying to make lower cost locations a thing. Big lol there

....unless you mean fab outsourcing

WhyteRyce fucked around with this message at 22:31 on Jan 6, 2021

movax
Aug 30, 2008

WhyteRyce posted:

Never heard it was over an outsourcing argument but Intel does love trying to make lower cost locations a thing. Big lol there

....unless you mean fab outsourcing

Probably fab outsourcing I'd imagine.

Just grabbed a E3-1285 v6 off eBay to max out my NAS board (X11SSL-CF) with the last/fastest processor it can take, plus I wanted a iGPU for QuickSync. Don't know if it's sad or funny that Skylake-based Xeons have been essentially buildable / usable for most server builds for like 5 years now. Long-rear end run for a CPU uArch.

Thinking about it, I guess Sandy Bridge started development when Dubya was still in office — if you go back to project starts, we probably start to get close to the decade mark for lifetime of some of these processors.

FuturePastNow
May 19, 2014


shrike82 posted:

lol I didn’t realize Jim Keller rejoined Intel and left again purportedly due to an internal argument about outsourcing.

We don't know why he left or what he was working on. It is a mystery!

NewFatMike
Jun 11, 2015

FuturePastNow posted:

We don't know who he was... Our what he was doing... But his legacy is hewn into the living rock of silicon

shrike82
Jun 11, 2005

FuturePastNow posted:

We don't know why he left or what he was working on. It is a mystery!

https://www.reuters.com/article/us-intel-thirdpoint-exclusive-idUSKBN2931PS

quote:

Exclusive: Hedge fund Third Point urges Intel to explore deal options

In June, it lost one of its veteran chip designers, Jim Keller, over a dispute on whether the company should outsource more of its production, sources said at the time.

who knows but it wouldn't surprise me

WhyteRyce
Dec 30, 2001

Keller isn’t an Intel lifer and doesn’t hold any affection to Intel fabs, so I can see him thinking they need to go pound sand for one reason or another. And I can see the org that birthed BK onto the company has an...entrenched and...political mindset

shrike82
Jun 11, 2005

it's always fascinating to follow the implosion of a successful organization due to bean counters and office politickers taking over
you have to give microsoft credit for being able to renew itself especially when you look at other big tech cos from its era

movax
Aug 30, 2008

Speaking of Keller chat: https://www.anandtech.com/show/16354/jim-keller-becomes-cto-at-tenstorrent-the-most-promising-architecture-out-there

Feels like the real winner in all of this continues to be ASML, TSM, CDNS and SNPS. Goddamn I should have bought more TSM years ago.

trilobite terror
Oct 20, 2007
BUT MY LIVELIHOOD DEPENDS ON THE FORUMS!

WhyteRyce posted:

Keller isn’t an Intel lifer and doesn’t hold any affection to Intel fabs, so I can see him thinking they need to go pound sand for one reason or another. And I can see the org that birthed BK onto the company has an...entrenched and...political mindset

Reminder that Keller’s the guy Apple tapped back in like 2010 to build their silicon development division, and he oversaw the A4 and A5 rollout before going to AMD to oversee Zen

Outside of Intel’s own management I can’t think of any one individual with more of a hand in Intel’s current fate than him

in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

Rumor out of some Taiwanese ee forums was that the fab org was a complete shitshow on 10/7 and constantly lying about it and keller figured this out and wanted to fab out flagship 2022ish parts but was blocked by production execs because the fabs printed money.

OTOH, he said he left for a family health emergency and his grifter evopsych benzo addict brother in law is in the Toronto area post-coma as is his new job.

in a well actually fucked around with this message at 03:43 on Jan 7, 2021

trilobite terror
Oct 20, 2007
BUT MY LIVELIHOOD DEPENDS ON THE FORUMS!

PCjr sidecar posted:

OTOH, he said he left for a family health emergency and his grifter evopsych benzo addict brother in the Toronto area post-coma as is his new job.

Jim Keller and Jordan Peterson are brothers?

Kazinsal
Dec 13, 2011


Ok Comboomer posted:

Jim Keller and Jordan Peterson are brothers?

In-laws, I believe.

trilobite terror
Oct 20, 2007
BUT MY LIVELIHOOD DEPENDS ON THE FORUMS!

Kazinsal posted:

In-laws, I believe.

so maybe the family emergency was more to do with Peterson’s wife having terminal cancer (I guess she must be related to Keller by blood) than the whole Russia/Serbia affair

in a well actually
Jan 26, 2011

dude, you gotta end it on the rhyme

Kazinsal posted:

In-laws, I believe.

Yes, typo- edited.

WhyteRyce
Dec 30, 2001

My completely unsubstantiated and completely obvious take last summer was the fab org was lying like poo poo about anything and everything and that Murthy was rightfully unceremoniously canned for either going along with the bullshit or being incapable of sniffing it out after having them report to him

shrike82
Jun 11, 2005

obligatory

repiv
Aug 13, 2009

if intel cleaned their cleanrooms maybe the 10nm node would work better

Endymion FRS MK1
Oct 29, 2011

I don't know what this thing is, and I don't care. I'm just tired of seeing your stupid newbie av from 2011.
I just saw my Micro Center has the 10600K for $229. How stupid of an idea is it to flip my 8086K and sidegrade?

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B-Mac
Apr 21, 2003
I'll never catch "the gay"!
Are you overclocking the 8086K? They are practically the same chip I’m not sure why you’re even thinking about buying it.

B-Mac fucked around with this message at 23:43 on Jan 7, 2021

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