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Combat Pretzel posted:I've seen some loose AM5 schematic about how devices are wired up. 16 PCIe lanes come from the CPU, eight go directly to a PCIe 16x, the other eight go through a "mux", which distributes eight to the first slot and eight to the second. But this isn't really a mux, right? Just a switch, so it's 16x or 8x/8x, but not load balanced on demand (say the device in the second slot idling, raising the first slot with the GPU to 16x intermittently)? No it would be determined on boot using presence detect if there is a device in the second slot it would fix the first slot to x8 and the second slot would get x8. Changing pcie width on the fly is not something that most OSes would tolerate well (requires a link retrain and possibly re-enumeration).
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Oct 25, 2021 17:33
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Combat Pretzel posted:I've seen some loose AM5 schematic about how devices are wired up. 16 PCIe lanes come from the CPU, eight go directly to a PCIe 16x, the other eight go through a "mux", which distributes eight to the first slot and eight to the second. But this isn't really a mux, right? Just a switch, so it's 16x or 8x/8x, but not load balanced on demand (say the device in the second slot idling, raising the first slot with the GPU to 16x intermittently)? AFAIK in pcie-land a "mux" is a simple chip -- it's multiplexing the 2 8x links together when operating in 16x single-GPU mode. Possibly also some of the PCIe bifrucation that's supported directly by the CPU on threadripper & Intel HEDT CPUs is the same type of circuit. And a "switch" is a much more expensive and complex chip that does do load balancing, the same way that the chipset chip can share the full bandwidth of its link to the CPU among many devices.
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Oct 25, 2021 17:38
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A (packet) switch will also show up in the pcie topology as well (device manager in windows or lspci in linux) with an upstream port and a few downstream ports that have devices attached. They’re not cheap ICs either so would only be on very expensive motherboards. The slot setup on that is definitely just a chip called a pcie signal switch (as opposed to the more complex packet switch) and hooks up like this:  From an app note by pericom here: https://www.diodes.com/assets/App-Note-Files/AN084-P.pdf Good breakdown on why it’s required (must be point to point connections with low signal loss, etc)
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Oct 25, 2021 18:06
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priznat posted:A (packet) switch will also show up in the pcie topology as well (device manager in windows or lspci in linux) with an upstream port and a few downstream ports that have devices attached. They’re not cheap ICs either so would only be on very expensive motherboards. Yeah -- those are common to support bifurcation / muxing between different slot configuration. Are PCIe switches actually that common still, with more and more lanes getting available from processors? I could see them becoming useful for some insane bandwidth bridging applications, but at that point I think you'll hit other limits. Just how many SAS3008s can you put behind a PCIe 4.0 x16 link and not be bottlenecked by that uplink???
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Oct 25, 2021 18:52
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movax posted:Yeah -- those are common to support bifurcation / muxing between different slot configuration. Are PCIe switches actually that common still, with more and more lanes getting available from processors? I could see them becoming useful for some insane bandwidth bridging applications, but at that point I think you'll hit other limits. Just how many SAS3008s can you put behind a PCIe 4.0 x16 link and not be bottlenecked by that uplink??? Yeah pcie switches are fairly niche but when system makers need them they are very handy. A lot of AI/ML stuff to scale out huge numbers of GPUs, and NVMe is hopefully going to overtake SAS at some point as various manufacturers are dancing around making spinning disks with nvme controllers connected by x2 pcie links as system designers want to get rid of SAS if possible. Switches will be pretty huge for that along with some specialized host bios changes to flatten the pcie tree addressing more to be able to use all the possible BDF addresses. Also switches help with host to host non transparent bridging for redundancy/failovers and in the future switches will be cxl compatible too for massive amounts of coherent memory spread around a rack. It’s interesting because as the hosts add more lanes it seems it is just more opportunities to hang more switches off it with more endpoints as usually the bottleneck isn’t the host but the number of endpoints it can handle. By making the lanes wide it can lead to a similar number of switches used but the latency is better because instead of having to go several switches deep it can just be each x16 of the 128 lanes going to a switch for fanout instead of a few layers required by the less lane ones like the 40 lane xeons. The reduced latency is huge for the AI/ML applications too. They do the majority of their traffic in small packet bursts (32 or 64 byte packets) to the cpu. Definitely a neat space although not really consumer focused.
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Oct 25, 2021 19:35
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So Zen 4 is rumored to have 28 lanes, which still isn't enough to waste on giving 2 GPU slots a dedicated 16x+8x combo. So consumer mobos will still have the 16/8+8 and a multiplexer chip. I dunno how they'll arrange them -- if they're gonna continue using a repurposed Zen IO die as the chipset, I could see putting an 8x link to the chipset being a good idea because that chip should be powerful enough to divvy up bandwidth. Means you could see some really stacked high-end boards that would go up against intel HEDT stuff pretty well. But the simplest idea would be 16x GPU, 2 dedicated 4x NVMe slots, and 4x to the chipset.
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Oct 25, 2021 22:22
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In the end i guess multi GPU is dead so really anything beyond the current 24 lanes on Zen 3 is sort of gravy anyway for 99% of desktop users. Tbh I think the bigger question is whether AMD is gonna go for feature parity with intel and offer PCIe 5.0 to the GPU... not that it really matters for like, years from now.
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Oct 25, 2021 22:56
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Yeah, multi-GPU is done, I think now it's about 16 lanes for grapics and then as many x4 links as possible for storage
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Oct 26, 2021 06:51
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Anandtech/Dr Curtis have just posted an interview with one of the Zen architects. There's a bunch of interesting stuff in there. https://www.anandtech.com/show/17031/anandtech-interviews-mike-clark-amds-chief-architect-of-zen He confirms that some future zen design will be going wider on the decode width, with Zen 1-3 all being 4-wide. Pablo Bluth fucked around with this message at 20:09 on Oct 26, 2021 |
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Oct 26, 2021 16:35
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Pablo Bluth posted:Anandtech/Dr Curtis have just played an interview with one of the Zen architects. There's a bunch of interesting stuff in there. That was a great read. The stuff about Zen 5 at the end was a really effective tease. It'll be interesting to see what the landscape looks like H2 of next year, with Zen 4 vs whatever Intel has available then. I feel like chances are really good that I'll be going Zen 4, but since it's gonna be a mobo change no matter what I'm more willing than usual to evaluate Intel. Right now though they're still burning as much power as possible to get that single-core lead back, which I do not find compelling.
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Oct 26, 2021 19:43
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I'm finally watching the interview and they touched briefly on the canned K12 design, the ARM CPU. It was intended as a sister product to Zen. Maybe one day we'll see an ARM design come through.
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Oct 28, 2021 04:16
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V-Cache always going to be a thing going forward with the upcoming Zen3 variant, or is that just some extraordinary release?
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Oct 29, 2021 00:51
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Combat Pretzel posted:V-Cache always going to be a thing going forward with the upcoming Zen3 variant, or is that just some extraordinary release? It's a big deal, it's their last major line before they bring out zen4 (which presumably also has 3d v-cache) late next year. There were rumors of XT versions but they are strongly implied to have been cancelled altogether in favor of focusing on the 3d v-cache CPUs. There's also b-revision CPUs but those are simply a change in internal manufacturing process with no difference in performance, and nothing more. If you ordered a CPU recently it might even be one of them when it arrives. Zedsdeadbaby fucked around with this message at 04:43 on Oct 29, 2021 |
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Oct 29, 2021 04:28
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Combat Pretzel posted:V-Cache always going to be a thing going forward with the upcoming Zen3 variant, or is that just some extraordinary release? Whether its a "V-cache" specifically or something else, AMD (and basically the entire industry) has reiterated that their future is some amalgamation of 2.5D / 3D packaging and/or stacking technologies. It's gonna get weird.
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Oct 29, 2021 04:30
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Dr. Cutress seems to imply that v-cache actually being cache is a smokescreen and that the main benefit of chip stacking here is for topology benefits. He made a video on it. https://www.youtube.com/watch?v=8teWvMXK99I Ring bus is dead, long live ring bus.
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Oct 30, 2021 09:59
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Zedsdeadbaby posted:It's a big deal, it's their last major line before they bring out zen4 (which presumably also has 3d v-cache) late next year.
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Oct 30, 2021 20:41
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It's been confirmed by the vendors that Zen5 is 3D stacked with compute cores (and so power dense that they basically forces datacenter to go to at least in door water cooling), so maybe its more like it only being cache is the differentiator for Milan-X and the V-Cache consumer parts? Just guessing here.
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Oct 30, 2021 21:58
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Combat Pretzel posted:That's what I'm wondering about. V-Cache seems really only to be mentioned in the same breath as the upcoming Zen3 in Q1/22, but regarding Zen4, nothing. You'd think, if this is the new hot thing, that they keep harping on it. I don't think we know what zen4's big change(s) are. Baseless speculation ahead, it's likely 3d stacking L3 & a wider instruction cache & whatever other ipc squeezing tricks they can pull off with the extra space from the node shrink & potentially reducing L3 footprint. AMD prioritizes not having a gigantic die for their CPUs & maintaining a power efficiency advantage -- 3d stacking L3 will give them significant headroom in both of those departments with no cost to frequency or ipc. Zen5 seems like it is going to be absolutely disgusting if they really do go with a sandwich design. It's going to be like zen1 all over again. Where all the Intel leaks  They have to be up to something cool too.
Khorne fucked around with this message at 23:17 on Oct 30, 2021 |
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Oct 30, 2021 22:45
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Disgusting in a good way or bad way
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Oct 31, 2021 17:20
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ijyt posted:Disgusting in a good way or bad way I can't seem to find the patent from many years ago where they had a concept of placing passive thermal transport through-die, but they also have a patent for stacking multiple layers of cache + multiple layers of logic with power between and then using gates in the layers as peltier devices to control the flow of heat between layers based on which is running cooler or hotter. The first is a caveman approach that may or may not work well & presents its own engineering challenges. The latter is quite clever and broadly applicable. Although it does consume some power and generate some heat itself so its practicality is unknown. If practical, it will be really good with big-little designs, apu designs where the apu is not being used, or designs that have deliberate thermal headroom in certain layers/areas. Imagine the older intel CPUs that had built-in igpus, the cores near it would always run significantly cooler than the cores farther away. And that's with no active heat transfer. The other interesting thing is both approaches would work well together, but I suspect that they will not use both because one method is likely a dud or too much engineering effort. also I don't work in anything related to this so I might have gotten everything wrong 
Khorne fucked around with this message at 17:56 on Oct 31, 2021 |
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Oct 31, 2021 17:42
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https://twitter.com/HardwareUnboxed/status/1454778534929461249 Looks like there are still a few bugs when using Windows 11 with Ryzen.
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Oct 31, 2021 19:02
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A reformat fixes it, it seems windows still treats the CPU as the previous one in some ways, and there isn't really a way to 'uninstall' a CPU in the same way you can use DDU for GPU software as far as I can see. That is going to be a colossal pain for benchmarkers though.
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Oct 31, 2021 23:29
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Zedsdeadbaby posted:A reformat fixes it, it seems windows still treats the CPU as the previous one in some ways, and there isn't really a way to 'uninstall' a CPU in the same way you can use DDU for GPU software as far as I can see.  doubt this actually does anything though (but i did just do it 16 times)
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Oct 31, 2021 23:32
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Malloc Voidstar posted:
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Nov 1, 2021 00:43
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I always found that to be one of the more horrifying bits of Adventure Time. <shudder>
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Nov 1, 2021 02:07
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do we know if PS4's are still being produced? intuitively I would assume no, but given how so many games are still cross-generation due to limits on how fast PS5s can be manufactured and distributed, and as I imagine some people are still going to buy a [presumably cheap] PS4 just to have something to game on, I wonder if the calculus on this has changed
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Nov 2, 2021 15:40
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gradenko_2000 posted:do we know if PS4's are still being produced? intuitively I would assume no, but given how so many games are still cross-generation due to limits on how fast PS5s can be manufactured and distributed, and as I imagine some people are still going to buy a [presumably cheap] PS4 just to have something to game on, I wonder if the calculus on this has changed In some markets it is. It'll probably be completely phased out of production by the end of the year.
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Nov 2, 2021 15:41
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Sony said they'd support the PS4 for three years. It was over three years between the launch of the PS4 and the PS3 being discontinued.
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Nov 2, 2021 21:29
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To that end:"gamesindustry.biz posted:The presentation wasn't all about PS5, with Sony also detailing its plans to make sure PS4 has its 'strongest ever tail'. Between that, the benefits of having a continuous x86 architecture path between generations, and the news that they have already sold 13.4 million PS5s worldwide, and you STILL can't seem to get one without fighting off scalpers, I could see the argument that Sony might have wanted to stretch the tail out longer, to compensate for chip shortage things and demand outstripping production, but that they were, in the end, being forced to put that end date due to partner demand to not have to keep accomodating the PS4 in perpetuity. In short: The calculus was probably at break-even when the PS5 launched at the end of last year, but tilts ever-more-rapidly in the PS5's favor as time goes on, despite Sony's attempts to keep it from going off a cliff. SwissArmyDruid fucked around with this message at 08:05 on Nov 3, 2021 |
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Nov 3, 2021 07:55
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MLID, so take it with a large grain of salt:
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Nov 4, 2021 02:38
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Dr. Video Games 0031 posted:MLID, so take it with a large grain of salt: Wasn't this guy wrong on his Very High Confidence predictions more than once? Like, shooting at 90 degrees off the target, wrong? Like, not even the right ballpark numbers/features, wrong?
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Nov 4, 2021 03:07
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Dr. Video Games 0031 posted:MLID, so take it with a large grain of salt: I wouldn't put much weight on speculating about memory channels. It would be really nice if consumers started getting 4 memory channels & more pcie lanes & full ecc support. I don't think we'll see it happen soon, although amd's embedded offerings support ecc so they clearly aren't too committed to gating it... Zen5 being more exciting is kinda known too, although there's a chance zen5 isn't more exciting. I put 0 weight on some of the things he speculated on in the video, like a 1024 core zen5d epyc coming out. I'd love to be wrong, because if that happens that means zen5 or zen6 non-d is going to be an insane desktop cpu. Apple entering the server market is pretty interesting. Khorne fucked around with this message at 03:22 on Nov 4, 2021 |
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Nov 4, 2021 03:16
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karoshi posted:Wasn't this guy wrong on his Very High Confidence predictions more than once? Like, shooting at 90 degrees off the target, wrong? Like, not even the right ballpark numbers/features, wrong? Yeah that's this guy.
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Nov 4, 2021 03:16
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Khorne posted:I wouldn't put much weight on speculating about memory channels. It would be really nice if consumers started getting 4 memory channels & more pcie lanes & full ecc support. bear in mind DDR5 goes to half-width but twice as many channels per DIMM... so "12-channel" is a 6-stick configuration. Consumers getting 4 channels next year is literally completely entirely confirmed since that's a normal 2-stick configuration.
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Nov 4, 2021 08:27
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Khorne posted:I wouldn't put much weight on speculating about memory channels. It would be really nice if consumers started getting 4 memory channels & more pcie lanes & full ecc support. I don't think we'll see it happen soon, although amd's embedded offerings support ecc so they clearly aren't too committed to gating it... That said, I sure hope there's gonna be fast DDR5 ECC rather sooner than later. It took its sweet time for there to be official DDR4-3200 ECC modules. Combat Pretzel fucked around with this message at 23:21 on Nov 5, 2021 |
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Nov 5, 2021 23:16
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Well the price cuts are finally, finally starting! 5800X is down to $300 at Microcenter, making it just $20 more than the 5600X. For once, the 5800X makes a lot more sense than the 5600X… until those prices get cut too. 10700K and 11700K also got big cuts, to $250 and $300 respectively.
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Nov 6, 2021 18:16
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AMD just announced:
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Nov 8, 2021 18:47
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I'm really curious to see what this means for the Zen4 Ryzen lineups, since a 96 core Genoa pretty much confirms a new 12 core CCX. Lots of interesting combinations in there, and it also sounds like the Zen4c cores might be able to be used for a big.LITTLE setup as well.
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Nov 8, 2021 19:07
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Number19 posted:sounds like the Zen4c cores might be able to be used for a big.LITTLE setup as well. No, Zen4c is identical to Zen4 in terms of capabilities, but is space-optimized to be physically smaller (at the cost of clockspeed and power efficiency, anandtech guesses).
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Nov 8, 2021 19:22
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mdxi posted:No, Zen4c is identical to Zen4 in terms of capabilities, but is space-optimized to be physically smaller (at the cost of clockspeed and power efficiency, anandtech guesses).
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Nov 8, 2021 19:46
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