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Arzachel
May 12, 2012
It pulls 84W under max load, a decent low profile cooler will do fine, never mind towers. People just freak out whenever a CPU goes over 60C°

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Rakeris
Jul 20, 2014

Yeah I have mine under a Dark Rock TF 2 and it does amazing, way better than I expected when I initially bought it. (Running -20 on all cores)

kliras
Mar 27, 2021
speaking of cooling, do i need to add 10c to my fan curve in asus bios? pretty sure this thing triggers 10c above where it should with my fan speeds matching the 80c point rather than 70c, but setting my non-idle points to 80c and 90c is a bit excessive otherwise

i can never remember how you're supposed to set that stuff

i forgot why i stopped using fancontrol; then i set it up, and it broke my cpu_fan bios driver, and i suddenly remembered

kliras fucked around with this message at 19:00 on Sep 12, 2023

Klyith
Aug 3, 2007

GBS Pledge Week

kliras posted:

speaking of cooling, do i need to add 10c to my fan curve in asus bios? pretty sure this thing triggers 10c above where it should with my fan speeds matching the 80c point rather than 70c, but setting my non-idle points to 80c and 90c is a bit excessive otherwise

First and 2nd gen ryzens did a thing where CPUs ending in X had a +10C offset on the main reporting temp, but I'm pretty sure that stopped long ago.

Do you have hysteresis / ramp delay set on the fans?

kliras posted:

i can never remember how you're supposed to set that stuff

There's no one right way to do it. The defaults are made to work for the stock coolers, and so are usually pretty aggressive about spinning up because those don't have a lot of thermal mass. For aftermarket coolers you can up the temperature points or drop the speeds in some combination.

Otherwise, every combination of CPU cooler, fan, system, and person will have a different idea of what's best.

kliras
Mar 27, 2021

Klyith posted:

First and 2nd gen ryzens did a thing where CPUs ending in X had a +10C offset on the main reporting temp, but I'm pretty sure that stopped long ago.

Do you have hysteresis / ramp delay set on the fans?
it's a 5800X3D, and there's 7.7s hysteresis on the cpu fan, longer on chassis fans. and the spikes in hwinfo64 don't go above 70c, that's why it's weird it's hitting all the 80c rpm's instead

this x470 asus motherboard is a mess already, but i'm just wondering what the logic here. the reasons my fans were louder than i thought doesn't appear to be because of hysteresis or even thermals but because it uses the stress mode for 80c

and this is after a fresh repaste on the d15 and reinstall of the bios to fix the cpu_fan bios driver

maybe i'll try out fan xpert, having exhausted all the alternatives

Stanley Pain
Jun 16, 2001

by Fluffdaddy
5800X3Ds can spike hot. Don't worry about it.

MagusDraco
Nov 11, 2011

even speedwagon was trolled

Stanley Pain posted:

5800X3Ds can spike hot. Don't worry about it.

Mine sure loves to do that. I've paired it with a noctua D12L and it likes to average/just hang out at the high 70s to 80 for BG3 set at 120fps when in conversations without undervolting. Haven't actually checked with doing that yet.

I don't really understand how to use core cycler or other things to test an undervolt (and just setting it to -30 had it crash after a couple hours of ff14 so I turned that down to -15 for now. If it ever crashes again I'll just drop it to -10 or turn it off altogether.

Kibner
Oct 21, 2008

Acguy Supremacy
Core Cycler is easy. Just let it run overnight every night or while you are at work for like a week. If it reports an error on any core, then the undervolt is too aggressive.

It is highly annoying, though. I understand. I hated having to do it and just gave up on undervolting altogether because I valued stability more, especially since my machine is my WFH machine.

Happy_Misanthrope
Aug 3, 2007

"I wanted to kill you, go to your funeral, and anyone who showed up to mourn you, I wanted to kill them too."

VorpalFish posted:

There's been a lot of talk about igpu cannibalizing the low to midrange GPU market though, and that's going to need bandwidth if it's going to happen.

That's supposedly what Strix Point/Strix Halo APU's are supposed to address, albeit I suspect they'll at least start out as high-end notebooks. A 256bit LPDDR5 interface to on-package memory for ~270GB/sec bandwidth on the Halo would somewhat address the bandwidth issue, albeit would still need some infinity cache to not be a bottleneck.

Rabid Snake
Aug 6, 2004



gradenko_2000 posted:

Finally, a CPU that can run C°ntinuum: roleplaying in The Yet

Lmao this was good


Been running my 7800x3d for two weeks now, replacing my heater of a 9900k. I only have a 2080 Ti but I didn’t realize how much of a bottle neck the 9900k has become when it came to frame time. The stuttering is all gone in games like Baldurs Gate 3 and COD MW2.
I was so used to the era where you could keep your cpu for 5 years (got the 9900k late 2018) and not be too far behind. I didn’t think I’d get this much of a gain

kliras
Mar 27, 2021

MagusDraco posted:

Mine sure loves to do that. I've paired it with a noctua D12L and it likes to average/just hang out at the high 70s to 80 for BG3 set at 120fps when in conversations without undervolting. Haven't actually checked with doing that yet.

I don't really understand how to use core cycler or other things to test an undervolt (and just setting it to -30 had it crash after a couple hours of ff14 so I turned that down to -15 for now. If it ever crashes again I'll just drop it to -10 or turn it off altogether.
-20 is more of a conservative setting for a 5800X3D since it doesn't seem to mind undervolts at all. you can always try out something higher, but going -20 and doing an occasional corecycler stress test is probably fine. ironically, one of the thing that weren't working for me at higher (err, lower) settings was that the computer would bsod when being completely idle when it was on as i had guest over, so that's a thing to test too

kliras fucked around with this message at 10:33 on Sep 13, 2023

Dr. Video Games 0031
Jul 17, 2004

Curve optimizer undervolts are far more likely to cause instability in idle or light load situations than in full loads. I'm not really sure how good core cycler is at finding that type of instability.

Arzachel
May 12, 2012

Dr. Video Games 0031 posted:

Curve optimizer undervolts are far more likely to cause instability in idle or light load situations than in full loads. I'm not really sure how good core cycler is at finding that type of instability.

Core cycler loops single thread Prime95 and switches affinity between cores to test peak single core boost, I don't think it'll catch idle/sleep state instability

Klyith
Aug 3, 2007

GBS Pledge Week

Dr. Video Games 0031 posted:

Curve optimizer undervolts are far more likely to cause instability in idle or light load situations than in full loads. I'm not really sure how good core cycler is at finding that type of instability.

The thing that makes you crash from undervolt is transitions between high and low power consumption. The root problem is the CPU can change power use far faster than the VRM can change supply. During that interval your voltage goes off from the target -- load high to low you get overshoot, low to high you get undershoot.

Both are bad, undershoot causes crashes and overshoot can age or destroy silicon. So the system is calibrated low by default, with just a little bit of margin to cover CPU variance. This is why you can safely overvolt a CPU by a lot more voltage than you can undervolt. Offset undervolts are working with "how much better is my CPU than the worst case CPU that still passes QC?"



Undervolts cause crashes in low & light load because you have lots of very brief spikes in CPU load when you're doing stuff like loading webpages or whatever. You notice them more because the average person spends way more time running light. But the best way to produce them is some artificial process to flick rapidly between high and low power use.

Core cycler moves a workload between cores and periodically does short suspends of the processes. That produces a lot of high-low transitions. I don't know that it's the best way -- you could also try running prime95 with max power across all cores and wiggle the mouse. But it seems decent.

Rakeris
Jul 20, 2014

When I was initially undervolting and load testing I definitely ran into low load crashes that core cycler or prime95 didn't catch, took a while to figure out the negative offset each core would take. Then I updated bios and didn't take a screenshot of what I had each core set too....so I just do a flat -20, instead of a range from -30 to -20.

Took probably a couple weeks of off and on testing, while occasionally running into low load crashes. Not looking to go through that much work again, even though most of it was just setting up stuff to run in idle time.

BlankSystemDaemon
Mar 13, 2009



Arzachel posted:

Core cycler loops single thread Prime95 and switches affinity between cores to test peak single core boost, I don't think it'll catch idle/sleep state instability
By definition, adjusting affinity from one core to another is going to keep basically all the cores but one in one of the C states, as those are all per-core.

SwissArmyDruid
Feb 14, 2014

by sebmojo
Alright, THIS looks like it might be the next Steam Deck killer. https://www.youtube.com/watch?v=zd6WtTUf-30

Take one Framework mainboard, build into an enclosure with controllers, and you've got a steam deck you can upgrade or hand-me-down hardware into.

A ROG Ally is already $700, and the AMD 7840U Framework mainboard is also $700... but upgradable and replacable.

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

I will have a spare Framework main board (albeit Intel 11th I think) once I get the new one, but the rest of the build is beyond me. Alas!

Koskun
Apr 20, 2004
I worship the ground NinjaPablo walks on

Subjunctive posted:

I will have a spare Framework main board (albeit Intel 11th I think) once I get the new one, but the rest of the build is beyond me. Alas!

The maker of that does say they will be offering a kit for the conversion.

I wish they would opensource the plans though. Screen, battery, controllers, and speakers could be sourced rather easily. A case could be sourced or 3d printed. Since the framework setup is pretty much all-in-one, I'd guess the most work would be battery, video, and speaker connections and mounting. They said the controllers are bluetooth.

Perplx
Jun 26, 2004


Best viewed on Orgasma Plasma
Lipstick Apathy
That’s the worst screen to body ratio I’ve seen since like 2005.

Yaoi Gagarin
Feb 20, 2014

Perplx posted:

That’s the worst screen to body ratio I’ve seen since like 2005.

Crumple zones

Khorne
May 1, 2002

Dr. Video Games 0031 posted:

Curve optimizer undervolts are far more likely to cause instability in idle or light load situations than in full loads. I'm not really sure how good core cycler is at finding that type of instability.
Core cycler is fine for "will this application close randomly" or "will my system have stability issues".

It doesn't test well for "will audio crackle" or other extremely sensitive cases. My 7800x3d is technically stable with an all core -20 (hundreds of hours of core cycler/other tests, gaming, etc), but audio is inconsistent and will crackle randomly. It's especially tedious because I can't isolate it to a core to figure out if some cores need different values.

I set tjmax to 80 and all core to -12 and it seems fine, tempted to try -20 again with the 80 tjmax. My motherboard was setting 85 tjmax and this can cause crackling/etc according to oc enthusiasts even if it never shows at 80c or higher in monitoring tools. With 85 tjmax I needed -5 for no crackling.

Khorne fucked around with this message at 17:18 on Sep 19, 2023

kliras
Mar 27, 2021
cyberpunk 2077 2.0's new eight-core utilization is going to be a fun new stress test

BlankSystemDaemon
Mar 13, 2009



Khorne posted:

It doesn't test well for "will audio crackle" or other extremely sensitive cases. My 7800x3d is technically stable with an all core -20 (hundreds of hours of core cycler/other tests, gaming, etc), but audio is inconsistent and will crackle randomly. It's especially tedious because I can't isolate it to a core to figure out if some cores need different values.
I assume you've checked your deferred procedural calls and interrupt service routines using LatencyMon?

BlankSystemDaemon fucked around with this message at 19:16 on Sep 19, 2023

kliras
Mar 27, 2021
audio crackle can also happens if you set your buffer size too high in your audio interface settings

Khorne
May 1, 2002

BlankSystemDaemon posted:

I assume you've checked your deferred procedural calls and interrupt service routines using LatencyMon?
yes, the issue is related entirely* to undervolting the cpu through curve optimizer. If I set it to -5 or turn it off my audio is perfect.

* might be a combination of things due to hand-tuned memory, voltages, infinity fabric, etc, but I have things stable except when I mess with curve optimizer so I'm okay with blaming it on co. The solution to a stable -20 with no audio crackling could be adjusting vsoc/vddp/etc voltages, but I'm not really sure that's true given without negative co the current ones aren't a problem.

kliras posted:

audio crackle can also happens if you set your buffer size too high in your audio interface settings
or buffer size too low, or frequency high, etc. My mic never messes up. It's only output to my headphones.

I have it seemingly stable right now with -12 on co and 96khz & 192 buffer size. It's stable at this same settings with -5 co also (& at 128 / 256 / 512 buffer sizes), and that one is 24/7 stable with no audio issues. I only rebooted yesterday with -12 & 80c tjmax instead of 85 so I'm not sure yet if things are truly okay or if I'll get a 1/4th second crackle while watching a 30 minute video or something.

-20 with 85tjmax got pretty bad when the system was under load with crackling on all sounds playing but the mic still being crystal clear. Adjusting buffer size didn't really seem to help while it was happening. Setting frequency to 44 & adjusting buffer size might have helped, but the issue with that is it introduces significant latency to my final microphone output even if my interface drivers say it should have the same latency due to a smaller buffer.

Khorne fucked around with this message at 20:33 on Sep 19, 2023

BlankSystemDaemon
Mar 13, 2009



Khorne posted:

yes, the issue is related entirely* to undervolting the cpu through curve optimizer. If I set it to -5 or turn it off my audio is perfect.

* might be a combination of things due to hand-tuned memory, voltages, infinity fabric, etc, but I have things stable except when I mess with curve optimizer so I'm okay with blaming it on co. The solution to a stable -20 with no audio crackling could be adjusting vsoc/vddp/etc voltages, but I'm not really sure that's true given without negative co the current ones aren't a problem.

or buffer size too low, or frequency high, etc. My mic never messes up. It's only output to my headphones.

I have it seemingly stable right now with -12 on co and 96khz & 192 buffer size. It's stable at this same settings with -5 co also (& at 128 / 256 / 512 buffer sizes), and that one is 24/7 stable with no audio issues. I only rebooted yesterday with -12 & 80c tjmax instead of 85 so I'm not sure yet if things are truly okay or if I'll get a 1/4th second crackle while watching a 30 minute video or something.

-20 with 85tjmax got pretty bad when the system was under load with crackling on all sounds playing but the mic still being crystal clear. Adjusting buffer size didn't really seem to help while it was happening. Setting frequency to 44 & adjusting buffer size might have helped, but the issue with that is it introduces significant latency to my final microphone output even if my interface drivers say it should have the same latency due to a smaller buffer.
Out of curiocity, what kinda audio interface are you using?

Does it happen using PCI, or USB, or both?

Khorne
May 1, 2002

BlankSystemDaemon posted:

Out of curiocity, what kinda audio interface are you using?

Does it happen using PCI, or USB, or both?
USB, it's a scarlett 2i2 first gen.

I have game mode off & all usb power saving off for now.

Khorne fucked around with this message at 22:19 on Sep 19, 2023

Dr. Video Games 0031
Jul 17, 2004

Obviously take everything MLID says with a grain of salt, but his AMD and Intel CPU leaks are generally accurate, and these slides are probably legit:

https://videocardz.com/newz/amd-x86-core-roadmap-leaks-out-zen5-nirvana-zen6-morpheus-microarchitectures-detailed





MLID also suggests in that video that AMD might stack CCDs on top of the IOD for Zen 6 for direct silicon to silicon interfaces in order to cut down on die-to-die latency.

Seamonster
Apr 30, 2007

IMMER SIEGREICH
That would also be good for increasing the package height under the IHS as well, lowering the effective thickness of it and improving cooling?

Dr. Video Games 0031
Jul 17, 2004

Generally, I don't think die stacking has a tangible effect on package height. With or without 3D cache is a microscopic difference in height.

I wonder if we'll see a double stacking situation with 3D cache on top of CCDs on top of the IOD. Or maybe they'll just put the L3 in the IOD.

PC LOAD LETTER
May 23, 2005
WTF?!
If they're gonna double stack like that then I'd think they'll have to lower power/clocks (even with the process shrink).

Or is the IOD big enough that you can put a CCD and the L3 die side by side on top of it instead of all 3 on top of each other?

I suppose if the edges over hang they can just put a support underneath it if necessary. Can't be that hard or expensive to put a bit of aluminum under it if necessary.

Probably would be worth it at that point to make the IHS into a vapor chamber instead of a slug of solid metal. But then I think doing something like that on the X Zen4 chips now would've been a good idea (and I wouldn't have minded a shim + exposed die instead).

Cygni
Nov 12, 2005

raring to post

Dr. Video Games 0031 posted:

Generally, I don't think die stacking has a tangible effect on package height. With or without 3D cache is a microscopic difference in height.

I wonder if we'll see a double stacking situation with 3D cache on top of CCDs on top of the IOD. Or maybe they'll just put the L3 in the IOD.

The L3 in the IOD (or in Intel's case, the interposer) underneath the compute chiplets is the path that Intel seems to be taking with Lunar Lake and/or Panther Lake.

quote:

As Gelsinger puts it, “[...] that particular type of technology isn't something that's part of Meteor Lake, but in our roadmap, you're seeing the idea of 3D silicon where we'll have cache on one die, and we'll have CPU compute on the stacked die on top of it, and obviously using EMIB that Foveros we'll be able to compose different capabilities.”

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

PC LOAD LETTER posted:

If they're gonna double stack like that then I'd think they'll have to lower power/clocks (even with the process shrink).

Or is the IOD big enough that you can put a CCD and the L3 die side by side on top of it instead of all 3 on top of each other?

I suppose if the edges over hang they can just put a support underneath it if necessary. Can't be that hard or expensive to put a bit of aluminum under it if necessary.

Flip that idea on its head, IMO. Stacking is real bad for power, but SRAM is low power density, so... why not make the IOD and the L3 die one big die? Lay things out so there's only SRAM directly underneath the CCDs, push all I/O functions to the edges where there's no overlap. The heatspreader would be in direct contact with the CCD, so this would actually offer better cooling of the CCD than today's X3D products.

That does make the IO/cache die huge, but one advantage of it being mostly SRAM is that SRAM can have enough redundancy to be easily repairable to improve yield.

This is just speculation on my part. No idea if the economics work, no idea if there's some other fatal problem with the idea.

BTW, when there is a need to resolve overhang with a spacer, my guess is that package designers would use a blank piece of silicon rather than a metal like aluminum. This would keep the coefficient of thermal expansion of all the support materials for the die on top the same so that there's no bending forces as temperatures move around.

e: if only I'd read Cygni's post before writing this one, lol

BobHoward fucked around with this message at 09:26 on Sep 30, 2023

Arzachel
May 12, 2012

PC LOAD LETTER posted:

If they're gonna double stack like that then I'd think they'll have to lower power/clocks (even with the process shrink).

Or is the IOD big enough that you can put a CCD and the L3 die side by side on top of it instead of all 3 on top of each other?

I suppose if the edges over hang they can just put a support underneath it if necessary. Can't be that hard or expensive to put a bit of aluminum under it if necessary.

Probably would be worth it at that point to make the IHS into a vapor chamber instead of a slug of solid metal. But then I think doing something like that on the X Zen4 chips now would've been a good idea (and I wouldn't have minded a shim + exposed die instead).

The advantage of stacking the cache is that there's basically no latency penalty. Having a separate memory die on the interposer/IOD would be much less useful for CPU performance but would be great for GPU bandwidth, if they're going that route with APUs.

PC LOAD LETTER
May 23, 2005
WTF?!

BobHoward posted:

why not make the IOD and the L3 die one big die?
My understanding is thats a no go for AMD due to economics of a big IOD but conceptually what you're talking about sounds like it'd work out just fine.

BobHoward posted:

This would keep the coefficient of thermal expansion of all the support materials for the die on top the same so that there's no bending forces as temperatures move around.
Sure but I thought aluminum has minor thermal expansion at the temps a typical CPU would be running at? Isn't the epoxy or glue or whatever it is a bigger potential issue?

Arzachel posted:

The advantage of stacking the cache is that there's basically no latency penalty. Having a separate memory die on the interposer/IOD would be much less useful for CPU performance but would be great for GPU bandwidth, if they're going that route with APUs.
Yeah that is a great point. I don't think they care too much about APU iGPU bandwidth very much and are more interested in boosting general performance somehow someway so that would nix my idea.

Tuna-Fish
Sep 13, 2017

Another reason you want cache on the IOD is that SRAM doesn't really scale on any process past 5nm. No point paying extra for super fancy expensive N3E/N2 silicon if the L3 takes the exact same amount of space.

I think the IOD will be done on a (then) obsolete process like N4, making it a lot cheaper place to put the cache.

karoshi
Nov 4, 2008

"Can somebody mspaint eyes on the steaming packages? TIA" yeah well fuck you too buddy, this is the best you're gonna get. Is this even "work-safe"? Let's find out!
Don't stop until all space between CCDs and IODs is filled with fat SRAM stacks. Can you make the IHS out of SRAM?

Indiana_Krom
Jun 18, 2007
Net Slacker

karoshi posted:

Don't stop until all space between CCDs and IODs is filled with fat SRAM stacks. Can you make the IHS out of SRAM?

Terabytes of cache to make up for everything being programmed as a lovely web app.

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PC LOAD LETTER
May 23, 2005
WTF?!

Indiana_Krom posted:

Terabytes of cache to make up for everything being programmed as a lovely web app.

This is it.

This is the way.

Gentlement, we have the plan, now AMD need only execute on it~~

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