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Indiana_Krom posted:Terabytes of cache to make up for everything being programmed as a lovely web app. x86 needs to add javascript instructions like ARM did, it's falling behind the webshit curve
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Sep 30, 2023 20:33
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Indiana_Krom posted:Terabytes of cache to make up for everything being programmed as a lovely web app.
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Sep 30, 2023 21:03
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BlankSystemDaemon posted:Modern mainframes have over a GB of distributed L3 cache. https://www.anandtech.com/show/17323/amd-releases-milan-x-cpus-with-3d-vcache-epyc-7003 You can get 1.5GB of L3 cache in a 2 socket commodity server as of last year.
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Sep 30, 2023 21:08
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AMD Socket SP9 announced: - 65" diagonal - 2ch DDR3 - supports up to 8TB L3 cache - up to 20k cores - 3072 PCIe7 lanes repiv posted:x86 needs to add javascript instructions like ARM did, it's falling behind the webshit curve I've patented a CPU that runs webassembly opcodes directly. So many nodejses.
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Sep 30, 2023 21:19
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Twerk from Home posted:https://www.anandtech.com/show/17323/amd-releases-milan-x-cpus-with-3d-vcache-epyc-7003 L3 cache on POWER8+(?) is shared across all CPUs.
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Sep 30, 2023 22:41
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repiv posted:x86 needs to add javascript instructions like ARM did, it's falling behind the webshit curve The Arm "javascript instruction" (there's only one) is way less specific to Javascript than people tend to think - it's just a variant of the floating point to integer conversion instruction. Because JS has this idiotic thing where integers are represented as floating point doubles, it leans FP-to-int a lot, and building a variant of FP-to-int with the exact rounding mode and other behaviors needed by JS is a very low implementation complexity thing with enough reward to be worth it.
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Oct 1, 2023 01:01
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so what you're saying is that ARM didn't go far enough and x86 needs to invest more heavily in baking javascript specific logic into the ISA 
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Oct 1, 2023 01:05
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at one point ARM had a whole instruction subset for running Java, I believe. it’s a sickness otoh something like 5% of my (large, public) company’s total fleet CPU is consumed deserializing JSON, so some acceleration for that would be welcome
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Oct 1, 2023 01:16
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Subjunctive posted:at one point ARM had a whole instruction subset for running Java, I believe. it’s a sickness Use a better format
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Oct 1, 2023 01:19
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Sweeper posted:Use a better format ah, but public APIs roughly demand JSON could be worse, could be better
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Oct 1, 2023 01:24
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Subjunctive posted:at one point ARM had a whole instruction subset for running Java, I believe. it’s a sickness I just tried to imagine what I’d do if I came across something labeled a “JSON SerDes” on an SoC and it’s completely breaking my brain.
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Oct 1, 2023 01:27
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hobbesmaster posted:I just tried to imagine what I’d do if I came across something labeled a “JSON SerDes” on an SoC and it’s completely breaking my brain. we have put dumber things into computers, like PhysX hardware or segmented memory access
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Oct 1, 2023 01:31
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Yes that’s fine but SerDes means something different in hardware and the collision of terms would be upsetting Also memory segmentation as a general concept is an absolutely critical foundation of modern software security and Physx acceleration was just generic VLIW SIMD that became the normal way GPUs worked. hobbesmaster fucked around with this message at 01:49 on Oct 1, 2023 |
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Oct 1, 2023 01:46
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hobbesmaster posted:Yes that’s fine but SerDes means something slightly different in hardware and the collision of terms would be upsetting oh, indeed!
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Oct 1, 2023 01:49
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hobbesmaster posted:Also memory segmentation as a general concept is an absolutely critical foundation of modern software security It really isn't though? Only x86 uses segments anymore, and even it doesn't use them for much in long (64-bit) mode. Most RISCs (including Arm and RISC-V) don't support segments at all. POWER/PowerPC do, because IBM had to be weird, but that's all I can think of off the top of my head.
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Oct 1, 2023 06:03
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Yeah I mixed up the name with executable space protection in general.
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Oct 1, 2023 06:23
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BobHoward posted:The Arm "javascript instruction" (there's only one) is way less specific to Javascript than people tend to think - it's just a variant of the floating point to integer conversion instruction. Because JS has this idiotic thing where integers are represented as floating point doubles, it leans FP-to-int a lot, and building a variant of FP-to-int with the exact rounding mode and other behaviors needed by JS is a very low implementation complexity thing with enough reward to be worth it. Subjunctive posted:otoh something like 5% of my (large, public) company’s total fleet CPU is consumed deserializing JSON, so some acceleration for that would be welcome Over here, they want me to create REST endpoints on their i Series for all SQL queries I perform instead of just polling the DB2/z directly with ODBC. Of course I keep telling them to gently caress off. Because two thirds or more of the JSON is in field names and not values. Combat Pretzel fucked around with this message at 08:52 on Oct 1, 2023 |
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Oct 1, 2023 08:50
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I'm putting together a cheap PC for my daughter and bought a X370 mobo (ROG Crosshair 6 Hero), Ryzen 1700, and stick of DDR4 3600MHz CL18. Patriot Viper Steel DDR4 16GB (1x16GB) 3600MHz PC4-25600 Single Module - PVS416G360C8 Capacity: 16GB(1x16GB) Voltage: 1.35V; tested frequency: PC4-25600 (3600MHz), tested timings: 18-20-20-40 I am used to Intel platforms where you enable XMP and don't even think about it. For the life of me I cannot get this thing to run stably. I have tried 1) just selecting 3600 RAM speed in the BIOS 2) loading "Extreme Tweaker" profiles e.g. "3600 MHz 1.4v Samsung B-Die profile" 3) turning on "DOCP Standard" for the "AI Overclock Tuner" I know it doesn't really matter in the scheme of things but I supposedly bought a 3600 speed RAM so I'd like to get it running if I can. What's the idiots guide to XMP on AMD? edit: I don't know if this means anything, but it's also running at CAS 20, even at 2666MHz. In its JEDEC timings it has CAS 18 for 1333 and 1.2V, so I don't get why it's choosing so high? VVV huh, that makes a lot of sense then. wups ~Coxy fucked around with this message at 09:26 on Oct 1, 2023 |
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Oct 1, 2023 08:52
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~Coxy posted:I'm putting together a cheap PC for my daughter and bought a X370 mobo (ROG Crosshair 6 Hero), Ryzen 1700, and stick of DDR4 3600MHz CL18. Zen 1 had a pretty bad memory controller and I doubt it can do 3600 in any capacity. 3200 may be a stretch.
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Oct 1, 2023 09:17
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3200 was the number you were aiming for, and the memory controller on my 1000-series degraded over time. Only ever used the XMP profile.
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Oct 1, 2023 09:36
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Subjunctive posted:at one point ARM had a whole instruction subset for running Java, I believe. it’s a sickness intel did find some pretty significant wins by throwing AVX512 at JSON parsing https://lemire.me/blog/2022/05/25/parsing-json-faster-with-intel-avx-512/
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Oct 1, 2023 14:39
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repiv posted:x86 needs to add javascript instructions like ARM did, it's falling behind the webshit curve x86 literally already has the exact same "javascript instruction" that ARM added. In fact, they have had it since the 80's! BobHoward posted:The Arm "javascript instruction" (there's only one) is way less specific to Javascript than people tend to think - it's just a variant of the floating point to integer conversion instruction. Because JS has this idiotic thing where integers are represented as floating point doubles, it leans FP-to-int a lot, and building a variant of FP-to-int with the exact rounding mode and other behaviors needed by JS is a very low implementation complexity thing with enough reward to be worth it. The instruction can be described as: convert FP64 into a 32-bit integer in the same way that x86 does it. The reason this is important for javascript is that when Eich implemented integer ops for js, he just converted the float into an int, then did the op, and converted it back. This is a problem for ARM, because he did that on x86, what happens when a float is too big to fit into a 32-bit int is undefined in the standard, and x86 and ARM did different things. (x86 gives a result mod register size, ARM clamps to highest representable int.) Calling it a javascript instruction was just less embarrassing for ARM than calling it an x86 emulation instruction.
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Oct 1, 2023 14:47
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karoshi posted:AMD Socket SP9 announced: 
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Oct 1, 2023 15:04
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Tuna-Fish posted:The reason this is important for javascript is that when Eich implemented integer ops for js, he just converted the float into an int, then did the op, and converted it back. No, I worked on the internals of that engine with Brendan in the 90s and 2000s, and it had tagged ints for everything that fit in 31 bits. For integer ops that could over/underflow that range we did the math in double space and then converted back to integer if it fit, otherwise the result was a tagged pointer to a double. Integer ops that couldn’t overflow, like right shift, stayed in int space the whole time.
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Oct 1, 2023 15:50
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Subjunctive posted:No, I worked on the internals of that engine with Brendan in the 90s and 2000s, and it had tagged ints for everything that fit in 31 bits. For integer ops that could over/underflow that range we did the math in double space and then converted back to integer if it fit, otherwise the result was a tagged pointer to a double. Integer ops that couldn’t overflow, like right shift, stayed in int space the whole time. That's the later spidermonkey, which had fancy things like optimizations. In the original mocha codebase, when an integer op is executed, it unconditionally pops floats, converts them into integers, does something with them, converts the result back into a float, and pushes it. (MochaInt and MochaFloat are not some fancy types with logic in the casts, but just i32 and f64.) It did not stay that way for very long, but the original prototype written in 10 days in 1995 was successful enough that the later versions wanted to maintain backwards compatibility. Some people in a JS conference estimated that those 20k SLOC contain thousands of decisions made that need to be thought of for backwards compatibility, nearly each and every one made with the heuristic of doing whatever was the most straightforward thing so that the prototype could be shipped in 10 days. Tuna-Fish fucked around with this message at 21:23 on Oct 1, 2023 |
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Oct 1, 2023 19:23
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ah quite, I forgot about mocha; apologies
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Oct 1, 2023 20:57
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Is $350 USD a good price for a 7800X3D?
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Oct 4, 2023 20:27
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I paid $450 back in April so I'm gonna say yes.
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Oct 4, 2023 20:51
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I think that's the lowest price it's hit outside of maybe some Microcenter deal or similar.
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Oct 5, 2023 05:17
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AMD is rolling out a new AGESA version with support for Phoenix APUs: https://wccftech.com/asus-amd-agesa-1-0-8-0-bios-am5-motherboards-supports-ryzen-7000-phoenix-apus/ Phoenix is the codename for their Zen 4 + RDNA 3 APUs (e.g. 7840U). It has been a long time since AMD has released a desktop APU that is competitive with their mobile offerings, so this would be a big change. The most powerful desktop APU on the market still only has Vega graphics in it.
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Oct 5, 2023 08:31
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i got it (and a copy of starfield) for 380 a couple months back and liked it. it’s probably gonna keep declining in price over time so it’s a personal call but if you want one, that’s a lower price than it was earlier. not sure what other ways there are to approach the question
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Oct 5, 2023 19:06
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I'd been running 1.0.0.7c for a while, and while it did increase stability it's still not perfectly stable with 4x32GB at 4800mhz. It's been about three weeks since I bothered to upgrade and clocked the memory at 4800mhz (was running 4000 before) but I got a corrected error today. This is close to how it behaved at 4200 before the update - going multiple weeks without any errors - so I'm assuming it'll be stable at 4600 or 4400, so there is an improvement but I can't help being a little disappointed. On the other hand I did leave everything else, including voltages, on Auto and I don't think I got the "right" memory chips that keep zen 4 happiest, so maybe tuning or buying the right chips would have helped.
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Oct 8, 2023 05:10
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Has anyone been able to disable various amounts of 3D vcache to see how performance scales as cache increases for various workloads?
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Oct 12, 2023 22:47
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I don't think you can just arbitrarily disable chunks of cache.
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Oct 13, 2023 00:04
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There's good news for people who like ECC.
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Oct 13, 2023 16:16
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You just need to have a very steady soldering hand
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Oct 13, 2023 16:21
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Falcorum posted:You just need to have a very steady soldering hand Soldering is only if you want to test it.
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Oct 13, 2023 16:28
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Doesn’t DDR5 have ECC-lite or something?
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Oct 13, 2023 19:59
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Josh Lyman posted:Doesn’t DDR5 have ECC-lite or something? It has on-die but doesn’t report back to the cpu so no errors are logged and there is also no verification of the correct data actually getting back to the cpu.
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Oct 13, 2023 20:01
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yeah it’s like it has intra-DIMM ECC but not ECC from the CPU’s perspective
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Oct 13, 2023 20:07
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