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New Zealand can eat me posted:If you've only tried the XMP profile, try disabling XMP, manually setting the Memory Clock to 4000, leaving all of the advanced timing configuration (except procODT and your ram/soc voltage) to auto. Ryzen boards have gotten quite good at finding their own set of stable timings. Like I mentioned previously, CL14 3600 will run faster (by literally a couple nanoseconds, or even several depending on subtimings) than CL16 4000, so you might want to try for that instead. Very few things on desktops need that much memory bandwidth. If you're trying to optimize around the clock sync for the IPC bus then the higher ram clock is probably a better bet.
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Jul 18, 2018 14:57
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E: I misread and thought they were using 4 sticks for the test. It still doesn't make sense that he's having such a hard time keeping 3600mhz stable. I've built/configured two 2700X systems with b-dye and they've been solid so far. I really don't think they were both golden given the odds, what is this "Ram Test" E2: Looking at it again these motherboards are using bios w/ ancient agesa versions?? 1.0.0.0a and 1.0.0.2. We're on 1.0.0.6 now yeah? I would be weary to treat this as a definitive guide on Zen+ ram performance. BangersInMyKnickers posted:Very few things on desktops need that much memory bandwidth. If you're trying to optimize around the clock sync for the IPC bus then the higher ram clock is probably a better bet. ??? I'm not sure what you're trying to say but benchmarks (especially The Stilt's, linked one post above) handily demonstrate that tighter timings at lower clock speeds outperform looser timings at higher clockspeeds. By as much as 10% in some cases. New Zealand can eat me fucked around with this message at 15:26 on Jul 18, 2018 |
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Jul 18, 2018 15:12
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Stilt's benchmarks are testing against a single ram clock. Ram clock is coupled to IPC clock, and increasing ram clock (if you can get away with it) will reduce your IPC latency which may improve your workload even if it does nothing for ram bandwidth/latency due to the relaxed timings. This is a known property of the architecture.
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Jul 18, 2018 15:52
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New Zealand can eat me posted:E: I misread and thought they were using 4 sticks for the test. It still doesn't make sense that he's having such a hard time keeping 3600mhz stable. I've built/configured two 2700X systems with b-dye and they've been solid so far. I really don't think they were both golden given the odds, what is this "Ram Test" The AGESA versions reset when second-gen Ryzen parts came around. 1.0.0.2c is the most recent one for those chips. Are your DDR4-3600 settings Memtest stable or just "boots and runs apps" stable? RAM Test is this app: https://www.karhusoftware.com/ramtest/ It apparently does what Memtest does, just faster, or something. TheJeffers fucked around with this message at 18:06 on Jul 18, 2018 |
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Jul 18, 2018 17:19
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Khorne posted:This is true. I didn't really think voltage would solve it. He probably needs to either increase timings or lower clock speed (and maybe decrease timings?) I configured a higher voltage than the default in the settings because that's what the box said. I also had to manually enter timings, so maybe that's all gotten better with revision 2. Wish I could have stood to wait :|
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Jul 18, 2018 17:24
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Its WCCF Chinese rumor link and all but still relevant info so you don't have to click if you don't wanna: Zen2 will have a ~10-15% IPC improvement over Zen+ 16C/32T CPU's coming to AM4 64C/128T Epycs coming possible 8 core per CCX configurations No word on clocks but we still haven't seen anything that contradicts earlier comments by the GF fab guy either. If AMD can deliver on all that while Intel is still stuck they should do great in 2019 even if they get hammered in the GPU market.
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Jul 19, 2018 14:51
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I think all of that could actually come true but for 5nm in like 2022. None of it makes sense for 7nm.
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Jul 19, 2018 15:29
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16c AM4 would be pretty hot, but would likely require new motherboards with different TDP/VRM configurations. It would make more sense to go to 12c at the high end and segment 16+ for TR4.
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Jul 19, 2018 15:51
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PC LOAD LETTER posted:Wow, AMD is pressing the advantage. Any word on decoupling Infinity Fabric from the RAM controller?
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Jul 19, 2018 15:54
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A 64c/128t chip just sounds like science fiction to me after years where 6 and 8 core chips where what was classified as pretty high end.
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Jul 19, 2018 16:16
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Wasn't long ago that the rumour was 6C CCX.
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Jul 19, 2018 16:20
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dont be mean to me posted:Any word on decoupling Infinity Fabric from the RAM controller? Eh nothing is coming out, sorry man I gots nothin'. At this point I'd be baffled if they didn't decouple the IF bus from memory clocks and pump it up. Seems like the most straight forward way to get IF bus latency down but what do I know? ufarn posted:Wasn't long ago that the rumour was 6C CCX. Risky Bisquick posted:16c AM4 would be pretty hot, but would likely require new motherboards with different TDP/VRM configurations. Cool video on that VRM, relavent info starts around 7min in. Too bad the BIOS is kinda sucky. PC LOAD LETTER fucked around with this message at 16:38 on Jul 19, 2018 |
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Jul 19, 2018 16:26
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I remain hesitant, but an 8-core CCX part would be nice? 8-core CCX parts mean 8-core parts without having to use IF to go to other CCXes cores and reclaiming unified memory access.
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Jul 19, 2018 17:27
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Be interesting to see how higher core count CCX's get affected by having a single memory channel. I'm gonna hold off memory clocking further until Asrock release a bios that doesn't suck rear end. But it is at 3466 ~ 1.35v now.
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Jul 19, 2018 17:31
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SwissArmyDruid posted:I remain hesitant, but an 8-core CCX part would be nice? 8-core CCX parts mean 8-core parts without having to use IF to go to other CCXes cores and reclaiming unified memory access. Also it means an 8-core APU in a book ITX case.
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Jul 19, 2018 17:33
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dont be mean to me posted:Any word on decoupling Infinity Fabric from the RAM controller? AMD has said that the shared Infinity Fabric-DRAM clock domain choice is deliberate so they don't have to add buffers to the chip as they would if the clock domains were separate, so if they're going to decouple it there would have to be a compelling explanation for either use of the die area or for performance. I'd personally hope the Zen 2 IMC cares a lot less about the number and organization of DIMMs hooked up to it than I would for this shift in design.
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Jul 19, 2018 17:37
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ufarn posted:Wasn't long ago that the rumour was 6C CCX. That was just armchair architects spouting off, it never made any sense. How would you get a 64C chip out of 6C CCXs? And 8C is a 2x2x2 topology, while 6C is... nothing. They are either using an 8C CCX and keeping the same topology, or staying with a 4C CCX and doubling the number of CCXs. The former makes a lot more sense to me than the latter. Both AMD and Intel max out at 8 sockets, virtual sockets in the case of AMD. The small CCX means AMD doesn't really have a competitor for Intel XCC products, you can stack up to 224C in an Intel system and AMD maxes out at 64C. It's not a huge niche, but I have to imagine it'd be a lucrative one. Also, 8C APUs would be baller. But since AMD used a 4C CCX in Zen1, everyone insists they have to keep doing that forever. "Muh yields" or something. Since die harvesting obviously doesn't exist or whatever. See also: armchair architects who decided that since Ryzen used a MCM packaging, that AMD would obviously be introducing a MCM strategy with Navi as well. Since, y'know, it's not like people have been trying to make multi-GPU work for say, the last 20 years or anything, they didn't have the magic of Paul MaudDib fucked around with this message at 18:20 on Jul 19, 2018 |
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Jul 19, 2018 18:06
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10-15% performance improvement outside clocks would be kind of devastating for Intel, the 2700X now hits 177 cb15 single core, a 15% increase means matching an 8700k @ 4.7ghz. If it's independent of clocks, and a 5.0ghz core is possible, then it'd easily beat even an 8700k @ 5.3ghz.
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Jul 19, 2018 18:36
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ufarn posted:Wasn't long ago that the rumour was 6C CCX. The rumor mill these days is also saying that AMD has moved up the launch of 64-core server CPUs to the next generation rather than the generation after that (where the next generation would have been up to 48-core). I wonder if they weren't hedging their 7nm bets by designing 16-core dies (whether that's 4x4-core CCX per die or 2x8-core CCX per die) and then only expecting to only get 12 working cores on most chips but their 7nm yields are turning out so good that they feel they can launch with all cores enabled.
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Jul 19, 2018 18:54
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Seamonster posted:I think all of that could actually come true but for 5nm in like 2022. None of it makes sense for 7nm. why does Zen2 having a ~10-15% IPC improvement over Zen+ not make sense?
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Jul 19, 2018 19:06
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Intel is so turbofucked next year. AMD will have more or less equal single-threaded performance and double the core count, and Intel has absolutely nothing coming down the pipe that could remotely fix it. 8C Coffee Lake will be nice for gaming, but it's pretty much too-little-too-late. How in the world did BK keep his job for so long?
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Jul 19, 2018 19:34
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wargames posted:why does Zen2 having a ~10-15% IPC improvement over Zen+ not make sense? Because I don't believe they would prioritize it that much over ramping up clock speeds. For sure there will be IPC improvements in Zen2 but, educated guess and trend (admittedly small sample size) would suggest 10% at the absolute most in fringe cases. I just want those 16 threads at 5.0ghz drawing ~120W for $300.
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Jul 19, 2018 20:01
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On the off-hand that you missed it at $210 earlier in the month: R5 2600X for $188.99 https://www.amazon.com/AMD-Ryzen-Processor-Wraith-Cooler/dp/B07B428V2L That's 6/12, 3.6 base/4.2 boost, and a cooler. poo poo man, I paid more than that for a R5 1600 a year ago! SwissArmyDruid fucked around with this message at 20:11 on Jul 19, 2018 |
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Jul 19, 2018 20:08
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Paul MaudDib posted:See also: armchair architects who decided that since Ryzen used a MCM packaging, that AMD would obviously be introducing a MCM strategy with Navi as well. Since, y'know, it's not like people have been trying to make multi-GPU work for say, the last 20 years or anything, they didn't have the magic of It's more to do with the performance of the interconnect. AMD was prototyping a MCM design all the way back with Cypress, but HyperTransport maxed at 25.6 GB/s, and it was pushing at the limits of SerDes design and the transistors themselves to do so. The per-channel memory bandwidth of Cypress was 38.4GB/s, so even using one link per memory channel, that'd be a huge drop in performance. Looking at the RX 580, since that sort of midrange design is exactly what would be used for the component dies of such a design, it also has four channels of memory but now with 64 GB/s of bandwidth per channel. The intra-socket component of Infinity Fabric, running at 1333 MHz as in the case of Epyc/TR with DDR4-2666, has 42.6GB/s of bandwidth, but it is designed to be flexible with clock speed and I don't doubt that it would be possible for a GPU to clock it at 2000 MHz, which would mean that each link would be equivalent performance to a channel of memory, which is how they are allocated in the CPUs.
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Jul 19, 2018 20:13
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Sli on package is only one possible configuration. It's the conceptual easiest but has lost out in the market since it sucks to program for. I suspect any MCM style GPU will have to hide that it's a MCM and simply figure out a scaling method that is transparent which is gonna be really hard.
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Jul 19, 2018 21:11
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Sinestro posted:It's more to do with the performance of the interconnect. What Sinestro said, plus IF on CPUs has to inherently be flexible to allow for all the various different RAM timings involved with grabbing any pair of sticks of DDR4. I believe that given a fixed point in terms of GDDR5X/GDDR6/HBM2, they might be able to flip IF on its head to increase performance, because they only have the one point (or very few points) that IF has to work at. SwissArmyDruid fucked around with this message at 23:09 on Jul 19, 2018 |
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Jul 19, 2018 21:43
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Seamonster posted:Because I don't believe they would prioritize it that much over ramping up clock speeds. For sure there will be IPC improvements in Zen2 but, educated guess and trend (admittedly small sample size) would suggest 10% at the absolute most in fringe cases. I do not know man, i think lisa su is the anti-raja kodori and miracles can happen with zen.
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Jul 19, 2018 23:07
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Paul MaudDib posted:How in the world did BK keep his job for so long? Because Intel was "6 months away" from 10mn for 5 years.
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Jul 20, 2018 00:24
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Seamonster posted:Because I don't believe they would prioritize it that much over ramping up clock speeds. For sure there will be IPC improvements in Zen2 but, educated guess and trend (admittedly small sample size) would suggest 10% at the absolute most in fringe cases. Remember they were expecting to compete with a rapidly maturing Intel 10nm process and improved xxxxlake (Ice or Cooperlake I believe, not sure) core too by the time Zen2 is supposed to be out in Q1or Q2 2019. edit: a bigger L1 can only help but I always thought it was more of an issue keeping those 256bit vector units fed with wide enough data buses and fast enough caches that had low latency to be good for general purpose work loads still. 256 bit and 512 bit wide buses really eat some die space too I guess.\/\/\/\/\/\/ PC LOAD LETTER fucked around with this message at 04:26 on Jul 20, 2018 |
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Jul 20, 2018 03:38
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The only thing about those chinese rumors that seem on point is the increased L1 cache size yeah? Supposedly we're getting 256bit FMAC and AVX1/2 and those need more L1 right?TheJeffers posted:The AGESA versions reset when second-gen Ryzen parts came around. 1.0.0.2c is the most recent one for those chips. Are your DDR4-3600 settings Memtest stable or just "boots and runs apps" stable? They were ">2000 on Cinebench"/memtest overnight stable. It looks like it errors out on things that memtest doesn't. Idk if that's a good or a bad thing. Both people are the type to let me know immediately if their poo poo starts crashing and I haven't had any complaints yet *shrug* You seem confused about something. Just look at the charts, tighter timings are faster than loose timings and higher clocks. This was true of CL12 3200 over CL16 3600 on Zen, and the same is true for CL14 3466/3600 over anything higher at CL18 or 22 on Zen+ New Zealand can eat me fucked around with this message at 04:11 on Jul 20, 2018 |
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Jul 20, 2018 04:07
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Malcolm XML posted:I suspect any MCM style GPU will have to hide that it's a MCM and simply figure out a scaling method that is transparent which is gonna be really hard. Not really, at least in theory. IF allows them to connect with the same protocol as the network-on-chip (and the same bandwidth, if they're using enough links), and then the schedulers can distribute work to compute units on other dies (essentially) transparently, with their memory requests going out to controllers on other dies equally transparently. "At least in theory" is the key part there.
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Jul 20, 2018 04:27
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Paul MaudDib posted:Intel is so turbofucked next year. AMD will have more or less equal single-threaded performance and double the core count, and Intel has absolutely nothing coming down the pipe that could remotely fix it. 8C Coffee Lake will be nice for gaming, but it's pretty much too-little-too-late. How would 8C Coffeelake sell in the face of a cheaper Zen2 8C? Like, AMD might increase prices by 10%, but that's 349$ for a 3700X, compared to the likely 400-450$ for the inferior Coffeelake. I guess maybe Intel can sell Pentiums. EmpyreanFlux fucked around with this message at 00:13 on Jul 21, 2018 |
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Jul 20, 2018 23:54
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Quite well, inertia is a hell of a drug. I mean, we got a laugh out of "nobody ever got fired for buying Intel until now", but it's still a problem for AMD to overcome to shift OEMs main design focus away from the familiar Intel product lines they've been respinning for the past decade.
SwissArmyDruid fucked around with this message at 05:17 on Jul 21, 2018 |
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Jul 21, 2018 01:24
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Yeah don't forget Intel sold heaps of P4's back in the Athlon64 days. They lost marketshare but weren't in real danger of going under due to the fact AMD could never produce enough chips back then. The same (Intel not going away) will be true for the immediate future now due to market inertia. What is different now though is that AMD can use TSMC and GF to produce some of its parts and both have tremendous fab capacity so AMD can potentially meet much more demand. If AMD continues to execute well while Intel is stuck, especially if Intel's 7nm has big problems too, then things get interesting. Realistically speaking though I wouldn't be shocked if Intel uses the same dirty tricks that they used in the P4 days to keep AMD sales down. It seems though for now that AMD has gotten the jump on them with the Chinese liscened Zen CPU's so maybe AMD will be more proactive this time around. Who knows. Things are likely to get interesting either which way.
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Jul 21, 2018 03:10
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PC LOAD LETTER posted:Realistically speaking though I wouldn't be shocked if Intel uses the same dirty tricks that they used in the P4 days to keep AMD sales down.
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Jul 21, 2018 03:19
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So with their massively different R&D budgets, is AMDs ability to be competitive with Intel a testament to AMDs engineering staff, or are we so limited by physics that chip design is a lesser concern (and, ergo, there'd be lots of room for competition if not for ISA licensing)? Or is my understanding here completely off- base?
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Jul 21, 2018 03:42
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Some of you seem to be studiously ignoring that the "competitive" part remains heavily qualified by AMD managing mostly to suck significantly less than they insisted on sucking over the latter Phenom days and the entire *dozer architectures. There remains a ton of workloads and configurations where AMD is in no way the only sensible choice or otherwise dominant. People get to posting like it'll just be a massive shadowy Intel conspiracy preventing AMD from having 80% share next year, but the story is just that AMD has managed to not have another 10 years of using them being a bad joke.
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Jul 21, 2018 03:47
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PC LOAD LETTER posted:I wouldn't be shocked if Intel uses the same dirty tricks that they used in the P4 days to keep AMD sales down. Kind of too late to demand motherboards be white boxes. Intel isn’t the same type of litigious beast it used to be. No way could AMD divide their processors under the 3/5/7 classification without going to court under the old regime. Exclusive ownership of marketing ideas (including the marketing terms created for standard technologies) and then making the public crave those marketing slang terms was a big part of old Intel. These days, SMT-dubbed-HyperThreading is about all that remains. Otakufag posted:But it'll be the year 2019 and info moves way faster than in early 2000's, look at what happened to Nvidia GeForce Partner Program due to all the exposure and nerds crying. That only fell apart because Nvidia couldn’t keep it out of the hands of AMD, who knows a guy who will post any story they approach him with. Craptacular! fucked around with this message at 03:58 on Jul 21, 2018 |
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Jul 21, 2018 03:54
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Yeah, keep believing that the opinion of some bloke named Kyle swayed OEMs more than their own bean counters who obviously hate money.
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Jul 21, 2018 04:29
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fishmech posted:Some of you seem to be studiously ignoring that the "competitive" part remains heavily qualified by AMD managing mostly to suck significantly less than they insisted on sucking over the latter Phenom days and the entire *dozer architectures. There remains a ton of workloads and configurations where AMD is in no way the only sensible choice or otherwise dominant. In my defense, the question was asked "how would 8c Coffee Lake sell vs 8c Zen2?". Not knowing anything else about one side of that equation, it's why I said that inertia is the only thing that can be accurately relied upon as a limiter on AMD marketshare gains in the near future. Because people (read:OEMs) are lazy and don't move unless they've got an incentive to move, whether derived internally ("We have a prestige problem if we don't use the latest and greatest") or externally ("our customers are demanding AMD"). The math is going to come down to this: What's going to make the OEM more money? Reallocating funds to designing new AMD-supported platforms, with all of the growing pains that entails, or copying the old motherboard layout file from last generation, renaming it by incrementing the model number, and making modifications to the design to accept whatever the new Intel spec is? But inertia's exactly the right word to use in this case, because with enough force, inertia can be overcome. It just remains to be seen if AMD can continue to maintain at least competitiveness with Intel, and, as you say, developing products and configurations where AMD *is* a sensible choice or the overwhelming preference. So, knowing nothing else about GloFo 7nm, Intel's continued failure at 10nm, Keller joining Intel, Keller possibly being flexed to help on the CPU side (no actual proof of this, it's just that if he's already under Intel's roof, they'd be dumb not to make use of ALL of the man's talents) AMD's continued woes in the GPU realm, and a whole list of other mitigating factors, yeah, that's the only thing I can draw a conclusion on right now. Inertia. SwissArmyDruid fucked around with this message at 05:20 on Jul 21, 2018 |
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Jul 21, 2018 05:12
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