|
Sorry the N100 rules
|
#
?
Dec 4, 2023 19:56
|
|
|
|
| # ? Jun 12, 2024 04:45 |
|
|
Cygni posted:i think my fav type of catty tech marketing is the "pointing out something lovely a competitor does while also doing the same thing recently/currently". such a classic of the genre. Who can forget AMD's glue?
|
|
#
?
Dec 4, 2023 20:18
|
|
|
priznat posted:Is it recent that amd passed intel in market cap because I saw that today and was surprised. Maybe I just haven’t been paying attention. It's been a while, at least a year IIRC.
|
|
#
?
Dec 5, 2023 00:07
|
|
|
They just have to look at amd and nvidias gpu renaming
|
|
#
?
Dec 5, 2023 00:31
|
|
|
gradenko_2000 posted:https://www.intel.com/content/www/us/en/content-details/794505/core-truths-how-the-latest-technology-is-not-always-what-it-seems.html
|
|
#
?
Dec 5, 2023 01:06
|
|
|
Intel made a solid amd advertisement
|
|
#
?
Dec 6, 2023 05:54
|
|
|
Ryzen 7520U is bad, don't buy it get the Ryzen 7640U, thanks intel.
|
|
#
?
Dec 6, 2023 15:47
|
|
|
Intel: This AMD product has a 5 in it, which you can't trust because its a 5 and that means its old Intel: this is an i5, which you can trust, because it has a 5 in it, which means its the latest  source: intel dot com
|
|
#
?
Dec 6, 2023 16:36
|
|
|
It's dumb how good that branding works. There are constantly people saying that their laptop is still good because it's an i7 or i9 without having a clue that there are generations.
|
|
#
?
Dec 6, 2023 17:20
|
|
|
Beef posted:It's dumb how good that branding works. There are constantly people saying that their laptop is still good because it's an i7 or i9 without having a clue that there are generations. It's the end of the line for that branding. No more Core i7. Is a Core 5 Ultra better than a Core 7? Who knows!  Edit: maybe it's Core Ultra 5?
|
|
#
?
Dec 6, 2023 17:31
|
|
|
See also: a game like Genshin listing a "Core i5" as its minimum spec. Core i5 what? 8400? 6600? 2500K? Who knows! Branding!
|
|
#
?
Dec 6, 2023 18:54
|
|
|
SpaceDrake posted:See also: a game like Genshin listing a "Core i5" as its minimum spec. My absolute favorite spec in the Pre-Ryzen world was when games would list "Intel Core i7-4790K or AMD Equivalent".
|
|
#
?
Dec 6, 2023 19:01
|
|
|
when the devils can't
|
|
#
?
Dec 6, 2023 19:39
|
|
|
Twerk from Home posted:My absolute favorite spec in the Pre-Ryzen world was when games would list "Intel Core i7-4790K or AMD Equivalent". That was a perfectly understandable thing to write about 2013ish processors.
|
|
#
?
Dec 6, 2023 19:58
|
|
|
SpaceDrake posted:See also: a game like Genshin listing a "Core i5" as its minimum spec. Yeah that's a double-edged sword. You think you're just fine and don't need a new processor because stuff is still apparently targeting your i5/7/9.
|
|
#
?
Dec 6, 2023 20:22
|
|
|
Rocko Bonaparte posted:Yeah that's a double-edged sword. You think you're just fine and don't need a new processor because stuff is still apparently targeting your i5/7/9. That game might actually run on a 3.4ghz i5-650.
|
|
#
?
Dec 6, 2023 21:08
|
|
|
At least its better than the xeon naming A xeon platinum 8156 is better than the gold 6254r right?
|
|
#
?
Dec 6, 2023 21:46
|
|
|
Wild EEPROM posted:At least its better than the xeon naming there is plenty of dogshit naming to go around for all of the Big Three, which makes any of them going after each other over it a delight
|
|
#
?
Dec 6, 2023 22:18
|
|
|
RYZEN 5 ZEN 4 8 THREAD 3 SOME
|
|
#
?
Dec 6, 2023 22:44
|
|
|
-U
|
|
#
?
Dec 6, 2023 22:45
|
|
|
Beef posted:It's dumb how good that branding works. There are constantly people saying that their laptop is still good because it's an i7 or i9 without having a clue that there are generations. We shipped out new laptops at work and people who are supposedly developers were flipping out that they were i5 when their old ones were i7. Similarly I've had a Tech Lead search through all the ancient crappy laptops from one of our customers and select the one with the i7 sticker to give to a new starter with a straight face.
|
|
#
?
Dec 7, 2023 05:19
|
|
|
gradenko_2000 posted:https://www.intel.com/content/www/us/en/content-details/794505/core-truths-how-the-latest-technology-is-not-always-what-it-seems.html what the gently caress unprofessional boomer horseshit is this
|
|
#
?
Dec 7, 2023 05:42
|
|
|
Potato Salad posted:what the gently caress unprofessional boomer horseshit is this Apparently now silently deleted from their website. Some wing of Intel could find no one to stand up and say this presentation was a horrible idea lol.
|
|
#
?
Dec 7, 2023 05:52
|
|
|
It's one of the worst things I've ever seen a company do marketing wise. It actively makes their competition look better by simply them being not the ones that released whatever that is. Also they hammer home constantly how the latest isn't even good necessarily but then tell you to buy Intel's latest lmao They took a horrible idea then executed the horrible idea poorly and contradicted themselves. It's so bad, otoh, Intel finally gave me something to talk about Intel should just tell people it was meant as a private joke not meant for release, or a now fired intern was just getting practice making presentations. Or make up a cooler lie and say that an ARC GPU ai designed it
|
|
#
?
Dec 7, 2023 06:02
|
|
|
I knew it was a good idea to save screenshots. Too bad I didn't grab the whole thing.
|
|
#
?
Dec 7, 2023 06:08
|
|
|
It's all over YouTube and I'm sure it's easy to find in it's entirety elsewhere, I'm sure there's like 4000 reddit places with it
|
|
#
?
Dec 7, 2023 06:14
|
|
|
Steve from Gamers Nexus did a whole rant on it lol https://www.youtube.com/watch?v=xUT4d5IVY0A
|
|
#
?
Dec 7, 2023 06:53
|
|
|
Seems like arrow lake is indeed dropping hyperthreading but not adding rentable units yet https://www.hardwaretimes.com/intel-15th-gen-arrow-lake-cpus-wont-support-hyper-threading-or-rentable-units/
|
|
#
?
Dec 8, 2023 16:16
|
|
|
Paul MaudDib posted:Seems like arrow lake is indeed dropping hyperthreading but not adding rentable units yet I'd bet that Intel doesn't ship a server P-core platform in that position. I am uber-curious how the upcoming E-core Xeon platform gets priced, but I'm also preparing myself for list pricing that's completely unrelated to the much lower prices the handful of customers they designed this thing for will pay.
|
|
#
?
Dec 8, 2023 16:28
|
|
|
Honest question: how important is hypertheading? I seem to recall it being a big deal years ago, but I have no clue if it's even utilized anymore..? Have CPU speeds increased so much it's really no longer relevant?
|
|
#
?
Dec 8, 2023 20:49
|
|
|
slidebite posted:Honest question: how important is hypertheading? https://blog.cloudflare.com/measuring-hyper-threading-and-turbo-boost/ Big picture, in general, on average across workloads, hyper threading is a relatively power efficient way to improve throughput, but will not help tail latency that much. If you have high IPC, pipeline friendly code then hyper threading might hurt you, but that's mostly HPC type workloads. Turbo boost throws power efficiency in the trash and burns a lot of watts to go faster. Edit: Xbox lets developers choose between having hyper threading or 200MHz more clock. I would love to see the stats on what devs take, but I haven't seen anyone dig into it.
|
|
#
?
Dec 8, 2023 20:58
|
|
|
slidebite posted:Honest question: how important is hypertheading? CPU cores have increased so much that it's not as cool as it was. It's still very relevant and a big deal if you have more threads of work to do than your CPU has physical cores. But for desktop stuff, we are getting to the point where even midrange CPUs have more cores than our apps can use even without hyper-threading. That doesn't make it useless. You can do some useful tricks -- for example, mix lightweight and heavy threads on the same cores and run those at max boost, leaving other cores completely idle so you can put the more power & thermal budget into clockspeed. The rentable units thing is like, we have more silicon than we can shake a stick at so let's just give every P core a dedicated E core as a co-processor.
|
|
#
?
Dec 8, 2023 23:20
|
|
|
slidebite posted:Honest question: how important is hypertheading? I suspect they're getting rid of it, to avoid all of the issues that come from side channel attacks which SMT has enabled since 2005. Scheduling for HMP design still isn't viable though, because putting the work in the microcode (aka Intel Thread Director) - and I worry that it's an unsolvable problem, because it essentially involves balancing "finish a fixed amount of work quickly but use more power" vs "finish a fixed amount of work slower, but more efficiently". All of that is in the context of the fast path of the kernel scheduler (ie. the code that has to be the fastest, otherwise everything gets slowed down - which isn't a place you normally want to add heuristics, which is what the above amounts to).
|
|
#
?
Dec 9, 2023 00:12
|
|
|
slidebite posted:Honest question: how important is hypertheading? It depends on the design, and the extent to which it's hyperthreaded. Ryzen chips are very wide, and in their current implementation can lose upwards of 40% of their speed in multithreaded scenarios if SMT is disabled. Something like IBM's later Power CPUs or other server-targeted RISC chips can have 4-way or 8-way SMT, intended to saturate very wide CPU designs which are chiefly optimized for scenarios where the hardware threads are shuffling around relatively small data values but have lots of threads in motion. Think database querying, bulk code compilation and execution like Java backend apps. The potential for security exploits by keeping SMT is real, but I'd be surprised if everybody flat-out drops it, even in the medium term. To my knowledge AMD hasn't made a peep about removing it as an architectural feature, and Intel's got several incentives to drop it, both for simplifying the work of the Thread Director and for shoring up their reputation for security in the wake of Meltdown, Spectre, and Skylake's earned reputation for shoddy validation.
|
|
#
?
Dec 9, 2023 01:17
|
|
|
slidebite posted:Honest question: how important is hypertheading? It depends on the workload and how you design your core. SMT/HT comes from the desire to saturate idle execution resources - why not run a second thread on them? And in fact you can then build a much more powerful core with even more execution resources, and maybe schedule 4 threads, or 8! That way one thread could access all the resources if needed, but you also have good average performance too. The difference with CMT is the idea of dedicated resources in the thread. CMT is a really broad concept that ranges from totally independent cores that happen to share a FPU (like Sun Ultrasparc T1 “Niagara”) to bulldozer where it’s basically SMT but with an integer execution unit dedicated to each thread. Honestly the SMT/CMT distinction kinda is just marketing or conceptual, you can argue an 8core CCX with 1T ea vs a 1C with 8T, like Niagara. Where is the line between CMT shared units and an attached unit in the CCX? The problem is this is not free either, now you have to schedule two threads, and manage visibility of state and memory/cache across two threads, so the core is more complex and uses more area (but not as much as two cores), the cache design (vaguely remember reading you might need more ways?) and logic is more complex, and this extra poo poo you have to do comes at some cost to frequency as well. And especially now that spectre/meltdown have shown the dangers of exposing any sort of visibility between threads, whether that’s cache timings or execution timings or anything else. You have to be absolutely correct in your visibility as multiple threads speculate and reorder their execution, rollback, etc, and probably it leaks anyway because there’s no way for execution speed to not be visible, which leaks contention for resources (the old openbsd argument). So, how important it is depends on how you design your core. If you design a big fat core with tons of execution resources, then it’s more important - this is why zen always gained more from SMT than intel’s hyperthreads. You could also design a smaller simpler core without it, and it would probably even clock a bit higher, but this would reduce performance for a given level of speculation/reorder, because you’re not saturating your units constantly anymore. So you probably also need to be able to speculate more deeply. Which is why apple built a whole instruction set to let them do it… It also depends on your workload. If your workload is dense numeric math, that’s easy to saturate with. If it’s heavily speculative pointer-chasing stuff, that’s generally harder, you will be waiting on memory all the time and it’d be nice to have something else to do in the meantime (without swapping out the thread like a barrel processor, and losing all your context and cache locality). Or run at lower clocks and it matters less, but that trades peak per-thread performance. Or you can design a massive cache and offset that, but that has different consequences and tradeoffs. The general zeitgeist is shifting against shared resources anyway. Cores really probably should be private per-tenant, and really caches should be too (although that’s potentially a manageable attack surface if you get visibility exactly right). IBM’s design where there’s no L3 except for a pool of L2 you can steal from other cores looks pretty batshit in this context, incidentally, and they initiated that after knowing about smeltdown. There maybe still is a role for it in certain trusted environments - HPC, or oracle DB servers, business mainframes, etc. These things benefit much more from the improved efficiency from SMT and don’t really run multitenant or untrusted code (and things like user-controlled queries that leak timing can be mitigated by trusted, known code in the DB or OS). It’s not a coincidence that it’s POWER9 and ibm z/system still chasing that dragon (and sun/oracle before this). I hadn’t thought of rentable units/royal cores in this context. I’m not sure it changes anything as far as still being shared resources but tbh I’m not sure I really buy the idea of one thread executing on multiple cores (rentable units) anyway. “Royal cores” in the sense of a big core with several small cores attached makes sense. Having some shared resources that cores can request to become a de-facto big core makes sense, but you also leak some information about utilization. But I suppose leaking “I could get the big core 25% of the time” is less damaging than “I could get the other ALU 25% of the time”, and generally the more threads you have the more difficult I think it would be to extract data. Good luck extracting timing data with 7 other threads noising your measurements in SMT8 - SMT2 is the worst option as far as security. Like I said I’m not convinced on fusing units, that sounds incredibly finicky. But having some fixed shared resources that any core can rent is plausible I guess, and simply having fixed big+little cores in a cluster is very very plausible, perhaps easy (I strongly suspect AMD will mix dense cores into the ccx soon). All of this requires a lot more cpu-level control of scheduling (“rentable cores” in this version means you need to be able to move threads around inside a core/inside a cluster, to present what looks like a uniform 4-core ccx but internally is juking around threads on the big core when they’re ready) which is of course why intel is doing thread director even though that’s massive overkill for just normal symmetric SMT2. Yes, yes, MLID, but tbh he’s generally more accurate these days at least on coarse architectural details or specific hardware leaks. There really isn’t much of a source for anything else on this, given that it’s probably all 2+ years out. Just don’t pay any attention to performance numbers this far out. I don’t subscribe to all of his interpretations, my take is above based on what I’ve gleaned from what he’s spitballed in some other video that makes sense based on the general name and concept. There have been some leaked or mis-released docs relating to rentable iirc. There def seems to be some move to rethink the SMT and core complex idea. The gracemont 4-core ccx is already a first stab in this direction too. They really need to reduce the number of stops on the ringbus for consumer to continue to scale well, or move to a multi-ringbus system like ryzen. and getting a workable big.little topology is both an efficiency and a perf/mm2 concern as well. How do you make a mostly e-core that feels like a p-core? (7950X3D already fails at scheduling, will a dense die be like that too?) https://m.youtube.com/watch?v=ZuriVO-s26k Supposedly this is all Jim keller’s idea while he was at intel, so it has some cachet on that basis. However weird it seems, there’s gotta be some kernel of wisdom there. But, he also left pretty quick, not like he’s there overseeing the execution of the idea, and it’s not like intel is doing real great on that themselves either. And AMD has lots of great ideas coming in 3-5 years too. Paul MaudDib fucked around with this message at 05:53 on Dec 9, 2023 |
|
#
?
Dec 9, 2023 01:38
|
|
|
Also, like, bulldozer CMT is not really that different from SMT in the first place. Bulldozer was bad because it was designed at a low point in AMD’s history, not because it had one ALU pinned to each thread. Contrast Ultrasparc T1/T2 lol. The bottlenecks were things like frontend decode having to switch back and forth between servicing the two threads when fully saturated, and these were later mitigated especially in excavator (Bristol ridge). It wasn’t good but it certainly was a lot better than fx-8150. https://www.agner.org/optimize/microarchitecture.pdf This one tends to go down the memory hole but 8350 alone mitigated a lot of problems, the problem was by the time the 8350 came out it was going against ivy bridge and not that far away from haswell. Bulldozer wasn’t good against sandy bridge and steamroller wasn’t good against ivy/haswell, so they sort of melted together in a lot of people’s minds, but the increment between sandy bridge and haswell wasn’t really that small (especially in productivity with integer avx2) and steamroller made a fairly decent step over first-gen bulldozer too, it just still was too little too late. (Which coincidentally is also intel’s problem today, lol. Meteor lake even with the missed performance/efficiency targets would have been ok if it came out on-schedule in time for back-to-school shopping. Same for the server market, in both big cores and cloud cores… by the time intel gets it out, it’s ok, good at some stuff, but they can’t price it at a big premium against AMD’s.) Paul MaudDib fucked around with this message at 04:35 on Dec 9, 2023 |
|
#
?
Dec 9, 2023 02:03
|
|
|
Hasturtium posted:To my knowledge AMD hasn't made a peep about removing it as an architectural feature Seeing as they went in the direction of C cores that are full-fat on features but downclocked to hit the greater efficiency and compact size, they don't need to. For now at least. And since Intel still has a pretty big advantage on the software side, IMO this makes sense. Intel has the means to get major changes in OSes schedulers. AMD does not. So it makes sense for them to be conservative on stuff like very-heterogeneous P/E cores or Airbnb For Threads.
|
|
#
?
Dec 9, 2023 03:23
|
|
|
Klyith posted:Airbnb For Threads. AKA: How to get 27 different lovely electron apps to all play 'nice' with each other.
|
|
#
?
Dec 9, 2023 05:11
|
|
|
Klyith posted:Seeing as they went in the direction of C cores that are full-fat on features but downclocked to hit the greater efficiency and compact size, they don't need to. For now at least. AMD doesn’t need a separate e-core. Their internal microarchitecture is obviously a lot cleaner and better, iirc bergamo isn’t that much bigger than a sierra forest e-core but you also get 2 threads on it, and more total performance. Instead they have chosen to just maintain a relatively lean p-core, then densify it by using high-efficiency libraries in less critical places and reducing caches, plus a smaller avx unit. Zen4 p-core itself is very very small compared to intel. AMD is killing it in design efficiency. They have found a much better optimum and (speaking purely as an outside observer) appear to have much less legacy cruft, better building blocks for “product design process reusability”, and generally much better and more reliable execution. It takes intel so many tries to get a 2.5g nic right or get icelake-sp or sapphire rapids-sp out the door. Sapphire rapids workstation has a refresh coming for power/transient problem and it wouldn’t surprise me if intel has been having a lot of integration/packaging issues (I said this a long time ago and I think that guess is on the money). They actually are in such deep poo poo and it’s almost suicidal to take their foot off the petal on any of these. Even gpus are critical, where is intel’s grace/mi300x? Ponte vecchio is the product of the hour if it actually existed outside whatever rando contract.
|
|
#
?
Dec 9, 2023 06:04
|
|
|
|
| # ? Jun 12, 2024 04:45 |
|
|
Paul MaudDib posted:AMD doesn’t need a separate e-core. Their internal microarchitecture is obviously a lot cleaner and better, iirc bergamo isn’t that much bigger than a sierra forest e-core but you also get 2 threads on it, and more total performance. PV exists; it would’ve been competitive against A100s if they’d arrived when they were supposed to. Not so much against H100s or H200s or MI300s. They cancelled this years product (I assume because they were similarly a generation behind and losing money bc they had to pay tsmc to make most of the chips) but they have a 2025 datacenter gpu. Gaudi is their current AI play.
|
|
#
?
Dec 9, 2023 16:05
|
|
