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Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

longview posted:

If you're measuring a switching power supply output then RMS noise could be misleading since most of the "noise" could be switching spikes with a very high crest factor.
I remember evaluating some new DC/DC converter modules that had significantly better RMS noise parameters than the older models, the main difference was that the newer modules had faster switching so all the noise energy was at higher frequencies.
This pushed the noise beyond the measurement bandwidth of 20 MHz, number go down!

Not measuring anything like this. This is all just pretty standard audio op-amp stuff. Its all AWGN.

longview posted:

If you're being pedantic wouldn't noise spectral density be a better measurement anyway?

If you actually have the kit to measure this, sure. Otherwise, its just 10log10( noise_rms2 / measurement_bandwidth). And, you can get that RMS right off the scope.

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Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Stupid ADC question. I have a 16 bit ADC, in which a maximum analog input voltage of +/- 1V maps to integer outputs between +/- 32768.

Using the dynamic range equation of 6.02*16 + 1.76 yields a value of 98 dB. If I supply an input sine wave of 1 Vpeak, then I get a digital sine output of 32768 "V" peak. Converting this to power, I get 10*log10( Vrms^2) = 10*log10 ( (32768 / sqrt(2) )^2 ) = 87.3 dB. And, the minimum would be 10*log10 ( (1 / sqrt(2) )^2 ) = - 3dB. That's a total range of 90.3 dB, not 98 dB, which is what I would have expected.

What am I screwing up here?


KnifeWrench posted:

Does your colleague have a more digital background? Peak-to-peak noise makes sense if you're thinking about whether a signal is crossing logic level thresholds.

Ya, this is why. And it probably is the correct way, since we do care about crossing logic levels.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

longview posted:

Your initial equation is something I've seen before but not sure where - why add the 1.76 dB to the end?
Dynamic range is the difference between the maximum and minimum levels (which is always a bit of a fuzzy definition for real systems), 20log10(65535) = 96.33 dB. You won't find that extra 1.76 dB, I don't know where it came from.

I can't recall where it comes from either, but its in all the derivations. Its small enough that we can proceed with out it.

longview posted:

You're converting from peak-"voltage" to RMS then squaring it again, I've never done it that way. To convert between voltage and power levels in dB it's just a factor of 2 so you can do 20log10(rms value) and get the same result.


Your calculations are off because you're trying to work only in RMS values (for some reason I can't figure out) but your minimum level is still peak-peak.


20log10(x) = 10*log10(x^2), and RMS = Peak/sqrt(2)

I'm working in RMS because I care about power. RMS^2 is power (assuming a unit-1 resistance).

longview posted:

The maximum signal is 65536 peak-peak so you assume 32768/1.41 is the RMS value.

I think this is a point I'm getting confused on. The maximum signal is not 65536 peak to peak. The SPAN is 65536 units peak to peak, but the maximum signal is |+/- 1|. My ADC is only going to see values from "really close to 0" to a maximum of |+/- 1| V. It will not see a 2V signal. 2 over something very close to 0 is a different dynamic range than 1 over something very close to 0.


longview posted:

Maximum RMS value is then ~23170 (my calculator is set to 2 decimal engineering mode and I can't be bothered to change it).
The minimum level is 1 peak-peak (i.e. toggling between 0 and 1) and 0.5 peak, giving a minimum RMS of 0.5/1.41 = 0.355.
20log10(23170) = 87.3 and 20log10(0.355) = -9, giving a dynamic range of 96.3 in the most roundabout way I've seen yet :)

Peak of 32768 -> into RMS = 32768 / sqrt(2) = 23170 RMS, as stated. But Peak of 1 -> into RMS = 1 / sqrt(2) = 0.707, not 0.355.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Forseti posted:

It's the "quantization error in an ideal ADC" according to https://en.wikipedia.org/wiki/Effective_number_of_bits, but the citation is an ISBN so I'm not sure precisely where it comes from.

You can see it derived here:
https://www.analog.com/media/en/training-seminars/tutorials/MT-001.pdf

But lets not get distracted from the original question!

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

longview posted:

Your ADC will care about absolute voltage (or perhaps a current in some rarer cases), the only thing you accomplish by working with power is making the calculations harder (QED).

At some point I have to talk about power. In my application, I'm using the ADC output to generate plots of power spectral density, which have some meaning.



longview posted:

The maximum signal is a signal that covers the full span, if the span is 65536 units peak-peak the maximum signal is 65536 units peak-peak. These are literally the same thing.
Since the span in voltage is 2V then each of the 65536 units represents a voltage step of 30.52µV.

Yes, I understand that each digital delta represents a voltage delta of 30.52uV.

longview posted:

The smallest "signal" you could represent is a signal with e.g. a maximum value of 1 and a minimum value of 0 (or a signal changing between 32768 and 32769, same thing), the peak-to-peak value is 1 in that case. There's no "in-between" value for the ADC, that's the resolution.
Converting it to an RMS value of 0.355 or (incorrectly) 0.707 is an arbitrary re-definition that only exists in theory. The digital values the ADC would produce in that case would only be 0 and 1, no in-between.

I have to think about this, but, your very last statement is confusing as it seems to be invalidating your own analysis...?


longview posted:

You can't just pretend half of your signal amplitude doesn't exist, the ADC range is -1 to +1V, a 2V span. This is literally the same thing as a 0-2V signal if you ignore the DC component (which you'd normally do in an audio application).
The peak/RMS voltage consideration is useful for computing power in e.g. a resistive load, it's not useful for voltage-ADCs and digital systems and in fact seems to be actively confusing you in this case.

Per my comment at the start, I am interested in computing power in a resistive load (sort of; I'm interested in my signal's power spectral density). Maybe we're running into an XY problem here - I want to know the maximum and minimum power levels my ADC is sensitive too.


The maximum power I can detect would be a sine swinging from +1 to -1, representing an ADC output swinging from +32768 to -32768 (technically 32767), producing an RMS value of 23170, or a "power" of 10*log10( 23170^2) = 87.3 dB. The minimum signal I could detect would be some small sine producing a digital output swinging between +1 and -1, representing an RMS value of 1/sqrt(1) = 0.707 -> 10*log10(0.707^2) = - 3 dB. Thus, a power dynamic range of 90.3 dB.


...maybe there's a distinction to be made between voltage dynamic range and power dynamic range?


Ultimately what I want to do is add horizontal lines to my power spectral density plots indicating the maximum and minimum power levels my ADC is sensitive too.


Okay maybe this is what is comes down to:
I think what I'm interested is the power dynamic range between the maximum detectable sinusoid and minimum detectable sinusoid. Perhaps this is NOT the same as the commonly stated dynamic range equation

Cyril Sneer fucked around with this message at 19:27 on Apr 26, 2020

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Hey goons, I'm an academic DSP guy and my C is pretty weak. We have a firmware guy, but he's pretty green too.

We're working with the NRF52832 IC. We're taking in 16 bit samples and I want to map them into 8 bit samples, using the non-linear mapping depicted here:

https://imgur.com/a/H0f8GBX

Basically, a tanh look up table, mapping all 65536 values into 256 values. I proposed a LUT implementation, but my FW guy said there isn't enough memory to hold the table (no idea if this a legit claim or not...) Sampling rate is 11025 Hz, so the conversion method needs to be able to keep up with this.

I feel like this should be easily do-able, but I'm pretty naive with this stuff. Any guidance would be most appreciated!

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

ante posted:

Why are you trying to map 16-bit input to a 16-bit LUT, and then downscaling it?


Why don't you downscale it first? Just shift right by 8 bits, then do an 8-bit LUT

Edit: or even 9-bit if you're worried about aliasing

Not following you here (and maybe my understanding of a LUT is incorrect) but the idea is that you take the 16 bit value (which will fall between 0 - 65565) and just pull out the associated 8 bit value. The plot was just a way of showing the overall effect.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
I'm working through all your responses, thanks. One quick thing though:

Stack Machine posted:

The function you link to looks like it is intended as a form of dynamic range compression. The whole reason for doing this is to preserve information from the LSBs for very "small" values while keeping range for larger values, much like floating point.

Yes, this is exactly what I'm trying to do.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

ante posted:

No, that's what he asked for, but we don't know the application, so we don't know how critical accuracy is. I suggested throwing out the LSBs earlier.


Dynamic range compression. I want to preserve accuracy at smaller values.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Howdy goons.

The following figure shows the power spectral density of a system noise measurement (sensor -> amplifier -> ADC). You will notice it is not flat.
https://postimg.cc/nXP4KYm4/de0921b2

This figure shows the same data, now plotted in units of V/sqrt(Hz) and log of frequency -
https://postimg.cc/yJ3FLghw/ec38b2af

The linear roll-off is certainly indicative of 1/f noise, but it is dropping off at ~1dB/decade, unlike the typically quoted rule of -3dB/decade (though, I have read articles that generalize it to other proportionalities, eg., c x 1/fa, with c and a obtained through fitting). Anyway, has anyone seen this sort of thing before? I'm rather puzzled about what's causing it.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
I want to implement a low-pass filter with a non-linear/arbitrary group delay. That is, I specifically want to delay slower frequencies by a different amount than higher frequencies. There's lots of stuff out there on the group delay properties of different filters, but I'm not having much luck finding anything on how to specifically design for a desired group delay response. Any suggestions?

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
FIR theory time!

I have an I and Q stream that I pass through a Hilbert transform implemented as a digital FIR filter, resulting in forward and reverse audio channels. I then take the forward stream and pass it through a second FIR filter that does some filtering for pop/hiss reduction. The first Hilbert FIR filter consists of 2 sets of 21 taps -- one for the I and one for the Q (which is as actually just a delay), then, the second FIR filter is 11 taps applied to the one stream.

This approach is causing some performance issues and I'm wondering about more optimal ways of implementing it. Someone suggested combining them into one filter, but naively, combining two series FIR filters into one would just result in a single filter of size (11 + 21 + 1 = 33) taps, which doesn't save me anything.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Forseti posted:

I have no idea in terms of filter theory, I assume you're taking advantage of all the features of your DSP in terms of vector instructions and optimal data representation/organization for the architecture? How do people typically implement DSPs in the real world, do you just use a library that you can expect to be pretty well optimized?

Can any of it be offloaded to the analog domain as a prefilter?

Also, I love (seriously) how advanced the "Learnining electronics" thread gets :D

This isn't being done on-chip, but rather in place old iOS world. Literally, its implemented as Xout = sum( Yi*Ci), where Yi, and Ci, are the input samples and coefficients respectively.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Can anyone clarify these ADC specs? Analog inputs, top-two pages:

https://www.ni.com/pdf/manuals/374372a.pdf

It states a bandwidth of 300 kHz, and yet a max sampling rate of 100 kS/s. I suppose the 300 kHz could represent the physical hardware LPF cut-off, but if the sampling rate can't go that high, this seems like a useless specification. This also plays into the listed system noise value of 0.4 mVrms, wherein its not clear which bandwidth this is based on.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

KnifeWrench posted:

Apparently it's an analog frequency response thing, and not that uncommon to be much higher than practical (probably to keep the knee far away from the usable measurement range):

https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/141789/what-is-adc-bandwidth

Thanks, interesting. I'm usually used to seeing this in reverse - a sampling rate that exceeds the stated bandwidth, eg.,, scopes with a 70 MHz bandwidth but a 2.5 Gs/s sampling rate. I understand the reasoning for this, so my posted example was confusing.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Question about RF switches / relays -

I have a situation where I want to toggle between one of two loads into a VNA. A SPDT - where the two load returns would be common - would seemingly be obvious for this. But I'm curious if there is any reason or consideration for a DPDT arrangement, where both the signal and return path for each load could be switched in independently. This is at 4Mhz so not particularly high frequency, and the loads are actually just two transducer sensors (basically can treat as lumped elements).

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Working on a project where I want to read 20 sensor outputs "simultaneously". The outputs are all slowly varying DC, and I figure a sampling rate of ~2 Hz per sensor should suffice. My thinking was to use a 24-pin analog mux controlled by an MCU to iterate through each channel (at about 40 Hz). In looking at spec sheets, I'm surprised how high the on resistances are -- like 100ohms or more. I don't really know where I'm going with this, other than to say I thought this was weird.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

longview posted:

Standard old-school CMOS switches are like that, you can get higher performance ones at a cost. For high voltage use (i.e. +-15 V) the ADG45x is a good choice, there are also low voltage variants with similar performance.
I actually built (professionally) a 32 channel system capable of 14/16 bit operation with 600 Hz per channel a few years ago where I used 4x ADGxxx muxes (5 V variants, can't remember which).

Note that the on resistance is typically non-linear with signal level, which causes non-linear distortion, especially if you have any loading on the output.
My suggestion: if you have more than one ADC, you can split the design into e.g. 3x8 bit muxes with 3 ADCs to speed up the sample rate or give longer acquisition times.
Take special care with allowing sufficient settling times when changing channel - IIRC you should wait for at least 10x the slowest RC time constant of the circuit to get a ~16 bit accurate result. You can do a lot less settling for e.g. 12 bit resolution.

The fix for all your settling time and on-resistance issues is often to use a fairly high speed buffer opamp right after the mux. This means your mux output loading is low, resulting in low distortion, and fast settling.
Slew rate may be more important than actual gain-bandwidth here.
This opamp will also provide a consistent low impedance ADC drive, meaning you can run the ADC faster without sacrificing accuracy.
Also note: there will be some leakage between channels, if your source impedance is low this is typically not a factor. If the source impedance is high then you would need to buffer it before the mux (which is a huge pain for a 20 channel system).
And obviously ideally you should include a low pass filter per input with a cutoff below nyquist (adding an input cap also reduces the effects of charge injection when changing channels).
Consider oversampling and filtering digitally.

Hmm, lots of things I hadn't thought about - thanks!

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
We're doing some audio stuff at work and one issue we always have to contend with is high-amplitude low-frequency impulses saturating the ADC, which arise from things like physical tapping of the microphone. I don't want to reinvent the wheel here; I feel like this is something that the audio world has surely dealt with. I'm vaguely aware of things like limiting circuits and soft clippers, but looking this stuff up its largely presented in the context of intentional distortion. Any ideas or some keywords here would be most helpful!

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
oops, disregard.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Dominoes posted:

Design in a big label that says "Don't tap the mic"

Cojawfee posted:

Set up snipers to shoot anyone about to tap the mic.

lol

I should probably clarify that this isn't actually a karaoke night microphone or something. Its a wearable device that detects audio and does some DSP trickery. Because its wearable, its susceptible to getting knocked/banged/bumped and this causes high amplitude spikes that clip the ADC and ruin the signal.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

longview posted:

Question: Does this saturation cause other issues than hard clipping in the ADC? If not then I'd say a software fix might be preferable; it will involve clipping anyway so a DSP limiter is probably desirable anyway.
Another question: why is your analog saturation level higher than the ADCs? This potentially means dynamic range is being sacrificed; though I can see a design targeting optimal sensitivity ending up in this situation.

The hardware fix will be some variation of non linearity, hard or soft clipping is AFAIK typically just done with diodes; the higher the source impedance the softer they will clip.
Fixing it right at the ADC (ideal if there are issues beyond the saturation itself) would probably involve putting current steering diodes to the maximum positive and negative voltage the ADC can handle (and perhaps a slight attenuator before the ADC).



Yes, at its core its a dynamic range issue - we're going for sensitivity. Our signal of interest is quite weak, so our gain stage is designed to bring it into (more or less) the full range of the ADC. So, when large amplitude events happen, they saturate the ADC input.

I've seen this diode approach mentioned elsewhere but I'm not sure it'll really work. It seems you're just trading off ADC clipping for diode clipping. The issue with the clipping isn't component damage, its that under an FFT, it causes all sorts of artifacts -- presumably the diode clipping would do the same.

Cyril Sneer fucked around with this message at 20:20 on Jul 17, 2021

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Jonny 290 posted:

I'm thinking for the mic tapping problem that a highpass filter is in order. Is this intended to normally transmit the human voice? There's not really any useful information below about 120-150 hz or so, you can chop freely below there.

We have one around 150 Hz, but a real filter doesn't provide perfect attenuation, so big stuff can still get through. Additionally, the frequency content of these impulse events can be fairly broad.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

petit choux posted:

compressor/limiter is the first keyword that comes to mind. I used to be really partial to an old Symetrix model, the 525.

Yeah, I've been looking into compressor/limiters. This is for an IoT device so I can't stick a 525 inside it :)

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
I actually just stumbled upon these soft-limiter circuits which use parallel diodes across the feedback resistor to kill the gain when activated. Seems promising?

https://sites.google.com/a/davidmorrin.com/www/home/trouble/troubleeffects/distortion-overdrive/op-amp-distortion-and-overdrive

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

longview posted:

True, this is only necessary if the ADC were misbehaving, but clipping is correct behaviour when the input signals are too strong so adding additional limiting isn't going to help. Soft clippers may change the spectrum you get but it's still a non linear process that will always add distortion.

Yes, understood. It might be good enough though. You can always tap harder, but if we can get rid of / reduce the typical tapping, this would still be a nice improvement.

longview posted:

If you're doing spectral processing and the noise signal is an impulse you're kind of screwed regardless aren't you? Clipping will add more harmonic components sure, but if the impulses are broad band even before clipping there's no analog filter that can help with that.

Absolutely, which is why I'm exploring non-filter based strategies.

longview posted:

Can you do the real obvious thing and just detect clipping and ignore those samples +/- some time around the event?
In radio communications this is done using a noise blanker circuit that just detects the envelope of the total signal energy coming in (before narrow filtering) and disabling the receiver during those impulses. The super nice ones use a hardware delay line to make sure they can in fact ignore causality and respond "before" the impulse.
In this case it should be fairly trivial to do in a DSP.

This might work but doesn't really solve the problem. From a DSP perspective, blanked-out samples is the same as artifacted samples (i.e,. we can detect the artifacts, and hence clipping easily). The hope is to try to eliminate or at least reduce these events from occurring to begin with.


longview posted:

Another alternative I see is adding an automatic gain control circuit that can reduce the gain; this will need to either be slow to detect the event (i.e. it will "leak" some impulse noise through) or it can be made sensitive (using e.g. the derivative of the signal), but then it will also be sensitive to e.g. high frequency signals.

The problem with AGC is that our algorithms are dependent on absolute noise and signal levels so this would screw things up.

longview posted:

If you really need that signal with no lost samples then I'd say the most practical way of doing it is to add another ADC channel set to a lower gain (or even better, get a higher dynamic range ADC, and/or rethink the noise analysis of the circuit to see if you can't sacrifice some gain).
You could run the same processing on the other channel or detect when the high gain channel is saturated and switch to the low gain one during the event.

Now this is interesting, and might be doable. The IC we're using does actually have unused ADC inputs, hmmm.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Looking for something weird: I need a variable resistor in the range of ~10 - 100 ohms, and would be considered RF compatible (so not wire-wound).

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

poeticoddity posted:

Would either a trimmer pot or slider pot be suitable?

Yep.

Actually, this will probably do the trick -

https://www.digikey.ca/en/products/detail/tt-electronics-bi/93PR100LF/6155633

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
LTspice question!

I want to simulate a variable source impedance by scanning across the complex impedance plane (i.e., smith chart), then run a noise analysis at each test point. I know the step directive is a thing, but I'm not sure how to handle this case where there are 2 parameters to change, AND, how to deal with the capacitive and inductive halves -- can I specify a reactance explicitly instead of a component value?

Alternatively, I'm vaguely aware that LTspice can pull values from external files - maybe I can generate such a file that iterates through my desired range of values?

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Stack Machine posted:

If you have multiple .step commands they will be nested, or if you want to do some parametric curve around the impedance plane you can step one parameter and then compute the R/L/C values based on that. If you want to switch from a capacitance to an inductance when the impedance goes negative, you can use the ?: operator in the inductance expression to make the C 0 when the impedance goes positive and the L very large when it goes negative.
Hmm, interesting idea, thanks.

I've tried to use multiple .step commands in the past and could never get it to work...

Stack Machine posted:

Remember that this is only valid in the neighborhood of one frequency value, since impedance is a complex-valued function of frequency, so it might be fine if this is a narrow-band RF thing, but if you want to do broad-band noise simulations you'll need some representation of the input network, not just the value of impedance at one frequency.

I only need it at single frequency value.

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Stack Machine posted:

If you're entering them in the schematic editor I think they have to be in the same text area.

Like, as part of the same text entry field? Or, like, it won't work if you move one too far away? I wouldn't put it past ltspice...

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Thanks, I got it to work. My problem was I was doing this:

https://electronics.stackexchange.com/questions/126659/how-to-use-step-param-with-more-than-two-parameters-in-ltspiceiv

which generates paired sets of values, rather than iterating over combinations.

Still trying to think of a clever way to do reactance-injection though.

Cyril Sneer fucked around with this message at 20:44 on Sep 18, 2021

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
SNR theory question for everyone. I've asked this around in some other places and always seem to get different answers. In the figure below, my signal is "broadband" and occupies bandwidth BW. Fn is my Nyquist frequency.

https://imgur.com/a/4nKFGma


SNR is typically defined as signal power over noise power, but it seems to me there are 3 different geometric interpretations for defining the integration limits (which, for my toy example, just becomes areas-of-rectangles).

Case #2 is treating everything within BW as signal, which is definitely not correct, so I think we can rule out this one.

Case #1 seems reasonable, but you certainly could have a signal power less than the noise floor, which this interpretation doesn't allow.

Case #3 seems reasonable, but its a bit weird in that it looks like you'd be double-counting that overlapped region in the signal power and noise power.

So EE goons, which one would you choose?

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
I'm a bit confused about the differences between (solid state) RF switches and more generic "analog switches":

I.e, something like this:

https://www.digikey.ca/en/products/detail/texas-instruments/TS5A3159ADBVR/936395

versus this:

https://www.digikey.ca/en/products/detail/analog-devices-inc/ADG919BRMZ/997619

The ADG919 is reflective, which is conceptually the same as the TS5A (unused leg is an OC termination). I suppose the ADG part is spec'd to much higher frequencies. Isolation, insertion loss type measurements could in principle be provided for the TS5A -- would they really be that different (to some upper frequency at least)?

More to the point, I'm working at 4 MHz and want to be able to switch several test elements to a VNA channel and I'm not sure which to pick (or something different altogether).

Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.
Quick question. I lost the IR remote for this RGB LED string:

https://ibb.co/3kTDXxR

The string itself is black and made of a thicker coated flex material, in contrast to those cheaper white strip ones. I've got a few of those as well, but none of their controllers work. I naively figured they all used the same chip, but evidently not.

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Cyril Sneer
Aug 8, 2004

Life would be simple in the forest except for Cyril Sneer. And his life would be simple except for The Raccoons.

Shame Boy posted:

You didn't actually ask a question :v:

Anyway that says it requires an RF remote, not an IR remote, so that's probably why the others didn't work :shrug:

Hah, good catch.

Yeah, I think you're right. I never realized they even used different technologies for this.

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