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LightRailTycoon
Mar 24, 2017
Off -lease $200 haswell i7s with 16gb of ram and an ssd for $200-$250 are pretty nice, too.

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LightRailTycoon
Mar 24, 2017

JawnV6 posted:

Not saying it's trivial but parallel x86 decode is absolutely possible? Why would you care where the last instruction ended, just compute all of them.

X86 instructions are variable length, so you need to decode all preceding instructions, or get wacky and speculate all possible instruction decodings.

LightRailTycoon
Mar 24, 2017

JawnV6 posted:

next time you can just go ahead and read both sentences instead of posting after the first one







you don't have to "decode all preceding instructions" you need to know how many bytes starting from and end+1. why would it matter how you ended up at any particular IP, are you decoding the instructions that lead up to a branch target?

You don’t know where each instruction begins until you have at least partially decided the preceding instructions.

LightRailTycoon
Mar 24, 2017

hobbesmaster posted:

Thats why it’s “speculative”

Right, on x86, you either run a single issue, sequential decoder, or you find every possible decoding, and speculate. On an architecture with fixed size instructions, you can decode in parallel, without speculating.

LightRailTycoon
Mar 24, 2017
On a fixed instruction size arch, say a64 arm, all instructions are 32 bits log, so you can take the stream of instructions, break it up into 32 bit chunks, and send it off to n simple instruction decoders, with minimal interaction between them.
On x86, instructions vary between 8 and 120 bits in length, you can't just do that. Instead, you have to settle for serial decoding and lose parallelism, or have a much more complicated decode, where all possible instruction decodings are tested for a given instruction stream.
This gives makes ARM work better with many short pipelines, and x86 work better with fewer, longer ones.

LightRailTycoon
Mar 24, 2017

forbidden dialectics posted:

I think what they're saying is that you don't know how many bytes :smug: the forward offset is to fetch the next instruction until AFTER you've decoded the current one, within a single pipeline. This is one of the inherent tradeoffs of x86.
Yes! Sorry my frustration about not being able to express my thoughts read as being lovely.

I wish I could find the article I read about speculative instruction decode, it was impressive.

LightRailTycoon
Mar 24, 2017
I just upgraded to 2.5gig symmetric fiber, and I really want an n100 with 2x10gbe ports, plus as many gig ports as I can have.

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LightRailTycoon
Mar 24, 2017
I miss green pcbs and beige cases.

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