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Alereon posted:Intel has also connected all parts of the CPU together using a high-speed ring bus, which is interesting because it physically sits on top of the L3 cache, like a highway overpass, allowing high-performance connectivity without taking up any room. I hope that isn't a quote from IDF, because it definately isn't true. SandyBridge cache slices sit opposite cpu cores on the ring; i.e. the core and the cache slice straddle the ring interface. There's additional wires to let a core talk to this nearest slice directly without having to emit a ring transaction. The thing I always found interesting was that the 3d graphics unit could also use the L3 cache.
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Sep 14, 2010 15:24
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Combat Pretzel posted:How can a mostly fixed function GPU be DirectX 10 compliant? (Apparently) Other companies reuse their programmable hardware for doing operations that could have been compliant if done in fixed function hardware. Or maybe he's just comparing Gen architecture with Larrabee. It's hard to tell with intel architects.
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Sep 14, 2010 18:49
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Alereon posted:. This is probably a direct response to Sandy Bridge's on-die graphics not supporting OpenCL, Can someone named JawnV6 confirm this because a certain architect suggested otherwise when he was lording over us how our 'other' graphics solution got poo poo canned
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Nov 16, 2010 05:02
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Sandybridge definately supports OpenCL
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Nov 18, 2010 23:22
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Combat Pretzel posted:From what I've read, their OpenCL implementation will use SSE and AVX, not the integrated GPU. What you read is bullshit; it really does use the Gen core. I wrote that after sitting through a technical presentation by the compiler team working on it
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Dec 8, 2010 05:44
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Misogynist posted:Has Intel announced even a tiny bit what their plans are for Sandy Bridge in the HPC space? Next HPC processor is Eagleton which is a 32 nm product with Westmere cores. A year after that is Jaketown which uses Sandybridge cores.
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Dec 24, 2010 08:07
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Combat Pretzel posted:Anyone knows whether there are virtualization improvements coming with SB? My Google-Fu leads me always to old Nehalem uArch slides and pages. Maybe some minor uarch improvements. I think VMCS cache is a feature for the Xeon sku only.
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Dec 29, 2010 19:36
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JawnV6 posted:
My spirit will be at hotdog island.
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Jan 3, 2011 20:20
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Roving Reporter posted:Anyone know the employee discount Intel gives their employees for hardware? My friend's brother works for Intel and I'm wondering if it would be worth it to ask him for a favor. If it's like last time it will be months before SNB shows up at the employee store.
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Jan 4, 2011 19:39
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While there Intel goons that work on related projects, or on different areas of the Cougar Point team; no one who was involved in directly in debugging this failure or in the design of the SATA analog circuitry has an SA forums account.
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Jan 31, 2011 20:21
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Combat Pretzel posted:and at some point just remove the x86 decoder. Apparently it is that piece which eats a lot of power. Yeah, no. Decode is literally the smallest cluster in any of our core designs. I'm loving tired of hearing this canard, even from people internally who should know better. Raptop fucked around with this message at 14:41 on May 19, 2011 |
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May 19, 2011 14:14
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