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Justus posted:Does anyone know much about the Wishbone interface? Wishbone is a bus interface, not a protocol per se. It's like the PCI bus on a PC. So Wishbone is used to describe how a peripheral is accessed (e.g. an N-bit address port, an M-bit data port, an enable strobe, a read/write flag, an ACK flag, etc). In most Wishbone systems, you'll have a soft CPU that's either Wishbone compliant or has some kind of a wrapper on its I/O ports to make it Wishbone compliant. When the CPU makes a memory call, it puts the target address on the address port, sends the right strobes/flags, and reads/writes from the data port accordingly. Then the requested device responds. I could be mistaken, but I'm not aware of any chips with hard-wired Wishbone peripherals. Wishbone is usually used as an interface standard in "soft" systems where the CPU and all peripherals are written in HDL and running on an FPGA. There are a bunch of bus standards in common use in the FPGA world. Wishbone is used pretty extensively by the Opencores guys, and I think Lattice uses Wishbone as the standard bus on their soft-IP cores as well. Xilinx and Altera use different buses. I've never worked with Wishbone, so I don't know the actual interface details. Check out the Wikipedia page on it, or maybe the Opencores page: http://opencores.org/opencores,wishbone Poopernickel fucked around with this message at 19:37 on Oct 28, 2011 |
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Oct 28, 2011 18:41
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Justus posted:Wow, thanks dude! I think I've got a pretty good handle on simulation now! And in just a couple of days!  Here's a quick sample testbench demonstrating a few techniques I wish somebody had shown me when I was just getting started, such as tasks and judicious use of the repeat() statement. http://pastebin.com/GWd7JwBG edit: made a couple of tweaks Poopernickel fucked around with this message at 21:17 on Oct 28, 2011 |
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Oct 28, 2011 19:26
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NM
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Oct 28, 2011 21:49
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Woah, looks like I was wrong - the Lattice Mach XO2 family does have some chips with hard Wishbone peripherals. Who knew?
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Oct 28, 2011 21:54
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Altium makes extensive use of wishbone. It is the basis of the GUI logic stuff and is used for all their IP modules. Different topic: The new version (its a few months old now) of Lattice's software is much, much better than the last version. It is all integrated now.
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Oct 29, 2011 00:09
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taqueso posted:Altium makes extensive use of wishbone. It is the basis of the GUI logic stuff and is used for all their IP modules. How does Altium's tool set compare with Xilinx EDK? Could I make a complete FPGA design without having to use any Xilinx-supplied tools?
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Oct 29, 2011 01:04
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Poopernickel posted:How does Altium's tool set compare with Xilinx EDK? Could I make a complete FPGA design without having to use any Xilinx-supplied tools? No, you have to have the vendor tools installed for whatever brand FPGA you are targeting. Altium uses them as the backend for the actual fitting/etc. I haven't used the Altium FPGA tools much beyond playing around with it. It seems pretty slick. You can make a PCB with an FPGA on it. Drop in a PLL block, soft-cpu, some peripherals, etc. Then write C code to run on the soft-cpu (they bought Tasking and use their compiler). All inside Altium. And the integration gets you some convenient things -- for example, if you pinswap on the PCB, references to that pin will change in the FPGA code. I need to get some free time to really dig in, it is very capable, but also fairly complicated.
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Oct 29, 2011 02:11
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Justus posted:Does anyone know much about the Wishbone interface? Like I said in my first post, you should just read through the milkymist source. It happens to use wishbone.
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Oct 31, 2011 06:22
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Is there a way to reference data with a new identifier without dedicating memory resources? I'm setting up an SPI transfer, and I'm getting 8 bytes at a time back from the module in a single 64-bit register called Data_RX. I'd like to reference 8 bits of Data_RX at a time with nicely named identifiers. Basically, what I'm wondering is if it's possible to simply use an identifier, let's say "word1" that simply references Data_RX[7:0], instead of having to store the data twice.
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Nov 4, 2011 20:32
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Justus posted:Is there a way to reference data with a new identifier without dedicating memory resources? Just declare a wire and assign it to Data_RX[7:0]. When synthesized, wires occupy no resources of their own, and because your assignment involves no combinatorial logic, the whole construct optimizes away.
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Nov 4, 2011 21:29
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ShoulderDaemon posted:Just declare a wire and assign it to Data_RX[7:0]. When synthesized, wires occupy no resources of their own, and because your assignment involves no combinatorial logic, the whole construct optimizes away. Oh yeah, of course! 
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Nov 5, 2011 01:05
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I saw a blurb on Migen in the opencores newsletter. Looks pretty neat, but I haven't really dug into it yet. https://github.com/milkymist/migen/blob/master/doc/migen.txt quote:Started late 2011 and still experimental, Migen is a Python-based tool that aims at automating further the VLSI design process. Sample code
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Feb 23, 2012 17:42
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taqueso posted:I saw a blurb on Migen in the opencores newsletter. Looks pretty neat, but I haven't really dug into it yet. Pretty exciting! I hope it makes timing closure less of a pain in the dick.
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Feb 23, 2012 18:02
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From the announcement I got the same feeling that OVM gives me. With that many macros and cruft between me and the simulator/generated hardware the complexity of debug shoots up. I'd rather spend extra time on legwork rather than digging through piles of goofy code I didn't write.
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Feb 24, 2012 00:56
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taqueso posted:I saw a blurb on Migen in the opencores newsletter. Looks pretty neat, but I haven't really dug into it yet. Looking forward to asking Sebastien about that when I see him in a few months at Notacon (he's doing a talk on Milkymist there). I don't think I would see myself using it at work though...debugging and simulation is already kludgey enough as it is, I don't think I'd want to add another layer in there. We have a Cadence Incisive license at the moment that we use for simulation. I thought the DDS IP that was mentioned in the newsletter looks pretty slick. Not to mention their reminder that 28nm FPGAs are finally going mass-market. I was tired of fellating the FAEs to get samples. e: then again, OpenCores is also full of gems like USB 3.0 Device and Hose IP Core. 
movax fucked around with this message at 05:53 on Feb 28, 2012 |
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Feb 28, 2012 05:50
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JawnV6 posted:From the announcement I got the same feeling that OVM gives me. With that many macros and cruft between me and the simulator/generated hardware the complexity of debug shoots up. I'd rather spend extra time on legwork rather than digging through piles of goofy code I didn't write. Gotta say that is my gut feeling, too. But I also really want someone to create a modern-feeling, higher-level hardware description language. If the piles of goofy code always worked right, no-one would care that they existed. I have a compsci background, so maybe I am biased.
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Feb 28, 2012 07:42
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taqueso posted:Gotta say that is my gut feeling, too. But I also really want someone to create a modern-feeling, higher-level hardware description language. If the piles of goofy code always worked right, no-one would care that they existed. I have a compsci background, so maybe I am biased. It's 6502 ML and not VHDL but you could probably mimic something like this: http://ahefner.livejournal.com/20528.html But since I love lisp I'm certainly biased.
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Mar 1, 2012 19:45
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This is kind of the FPGA thread. Anyone had a change to play with PCIe 3.0 IP from Xilinx or Altera?
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Apr 11, 2012 06:29
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movax posted:This is kind of the FPGA thread. Anyone had a change to play with PCIe 3.0 IP from Xilinx or Altera? I would be interested in hearing about it as well.
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Apr 11, 2012 14:46
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 Full speed gen3? What FPGA has 8GT/s IOs?
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Apr 11, 2012 19:16
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JawnV6 posted:
For some reason I misremembered the presentation I got from the sales reps as the mid-range models getting PCIe 3.0 as well, but it's just the Stratix V and Virtex 7 that sport Gen 3.0 support. (So, huge bucks.) Every Xilinx 7-series member at worst has Gen 2 PCIe (for some reason I thought Kintex-7 had Gen3). The Cyclone IV GX is currently pretty "cheap", but only does Gen1 PCIe.
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Apr 12, 2012 05:53
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Are there any FPGAs that have PCIe 1.1 compliant IOs and available IP that are not in a BGA package? I'd like to be able to hand solder these if it is possible.
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Apr 12, 2012 17:24
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taqueso posted:Are there any FPGAs that have PCIe 1.1 compliant IOs and available IP that are not in a BGA package? I'd like to be able to hand solder these if it is possible. The Cyclone IV GX TQFP *might*, it can do USB, IIRC. I'd assume the inductance of the TQFP lead itself severely curtails high speed protocols.
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Apr 12, 2012 17:28
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movax posted:I'd assume the inductance of the TQFP lead itself severely curtails high speed protocols.
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Apr 12, 2012 17:52
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Quartus II 12.0 came out a little bit ago. I'm seeing improvement in synthesis time (knocked a ~20 minute project down to 15 minute) and does a better job on timing (Fmax increased a bit). Of course, the device packs for 12.0 add support for all the new 28nm hotness. Anyone else play with it?
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Jul 13, 2012 00:43
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This isn't strictly about Verilog, but I guess this is kind of the de facto PLD thread as far as I can tell, so I thought I'd give it a shot... We're thinking about a new project here that would require 1 gigasample per second data acquisition. Because the device is battery-powered, I think the Lattice family still makes more sense for us than something like a Xilinx or Altera (both platforms tend to be way overkill in terms of area and I/Os for what we need, to say nothing of cost). So I was wondering if anyone had experience (or an opinion) on the iCE40 FPGAs? They're a good fit for us on area, cost, and IOs, and according to Lattice's Product Family Selector, they can achieve clock speeds up to 533MHz! When I look at the datasheet though, I get a bit confused. It says the max input clock frequency is 133 MHz, but that it has onboard PLLs with max output of 533...does that mean that I could generate 100 MHz from an osc chip, take it into clock pin on the iCE, PLL up to 500MHz, and then use 1:2 ddr gearing to acquire at 1Gbps? For that matter, the MachXO2 I'm already used to supposedly supports 1:8 gearing. Is there anything stopping me from just using that with a 125MHz clock? FPGAs are such fantastic tools for parallel computing, but they're limited in their clock frequencies compared to microprocessors. Is there a more conventional way to overcome their inherent serial weaknesses using parallel muscle?
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Sep 20, 2012 01:08
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Does anyone have a suggestion for a test fixture library for Verilog? Coming from software it feels like there should be 20 competing open source projects, but I can't seem to find anything.
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Sep 20, 2012 16:43
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taqueso posted:Does anyone have a suggestion for a test fixture library for Verilog? Coming from software it feels like there should be 20 competing open source projects, but I can't seem to find anything. I feel exactly like that EVERY TIME I try to find anything online that's been done in Verilog. It's like the internet is an HDL desert; it's difficult to find resources for anything PLD-related in general, and the number of experienced professionals posting anything useful is drowned out by the volume of newbies looking for help. In a weird way, it's almost like no one REALLY knows about this stuff. The best site I've found for open source HDL stuff so for is https://opencores.org. I don't think I saw any test fixture stuff there, but you might wanna take a close look just in case.
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Sep 20, 2012 17:42
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taqueso posted:Does anyone have a suggestion for a test fixture library for Verilog? Coming from software it feels like there should be 20 competing open source projects, but I can't seem to find anything. I'm not a SW guy, unfamiliar with the phrase 'fixture' library? Are you looking for a generic System Verilog testbench? Despite my stance in Feb, I've come around and OVM is pretty nifty. SVTB removes a lot of the previous drudgery of interconnects, OVM gets your brain in the right frame for HW validation. If you end up looking at anything titled "OVM-e", you did something wrong.
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Sep 20, 2012 18:13
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JawnV6 posted:I'm not a SW guy, unfamiliar with the phrase 'fixture' library? I mean a library to help with creation of a test bench or test fixture (terminology seems to be interchangeable in the HDL world, correct me if I'm wrong). I'm looking for something that can help with instantiating and ordering multiple tests, tracking and reporting successes and failures, etc. I believe the answer is that I need SystemVerilog, which has a bunch of support built in. But as far as I know, my tools will only do Verilog 2001. e: Could I use open source tools to do the testing in SystemVerilog, then synthesize the verilog in vendor tools? I'm not really aware of what is out there for open source verilog simulators.
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Sep 20, 2012 18:20
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Eh, if you're already in pure Verilog there's always Icarus Verilog. I've used it for hobby stuff before. I don't think you're going to find a generic testbench that you can plug into. They're generally simple enough to write your own unless you've got some massive amount of I/O to handle. To my knowledge there isn't a framework out there to run the tests for you and collect pass/fail,
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Sep 20, 2012 18:35
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Does anyone have suggestions for a cheap-ish FPGA development board for a newbie to learn on? I don't have any specific projects in mind and just want to get my feet wet with the technology, so anything with a few buttons/LEDs on the board to play with plus a not-painful programming toolchain would be great. Also, if any of the kits out there really suck I'd like to know which ones to avoid too.
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Sep 20, 2012 18:57
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I'm only familiar with the Xilinx side of smaller boards. Digilent makes nice ones that work with the free WebPack toolchain. I have a Nexys2. Do you have any Verilog or other HDL experience? All dev boards I've seen assume you know what you're doing. No "User Guide", just a datasheet and reference design if you're lucky.
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Sep 20, 2012 19:11
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Thanks for the link, something like the Nexys2 is along the lines of what I am looking for. Other suggestions still welcome of course. And no, no Verilog/HDL experience whatsoever - this is my attempt to learn the basics from the ground up. I do have an EE background and some programming experience so hopefully that will provide a reasonable base to build from.
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Sep 20, 2012 19:51
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JawnV6 posted:Eh, if you're already in pure Verilog there's always Icarus Verilog. I've used it for hobby stuff before. I don't think you're going to find a generic testbench that you can plug into. They're generally simple enough to write your own unless you've got some massive amount of I/O to handle. How do you structure your tests? I'd like to be able to have tests for each module (and tests for the top-level). Should I have a top-level testbench that instantiates a bunch of per-module tests and clocks each test module in turn? I guess they could all be in parallel... In the past I've only done simple per-module tests and run them each manually. I would really like to get everything as automated as possible this time. Honestly, I am pretty surprised how bad testing is for HDL. TDD/agile/unit testing is pretty huge in normal software development.
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Sep 20, 2012 20:15
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PDP-1 posted:Thanks for the link, something like the Nexys2 is along the lines of what I am looking for. Other suggestions still welcome of course. One thing I'd recommend is buying a Sega Genesis controller. You need to debounce it, but it's a lot better to drive a design with that instead of buttons and switches on the board itself. Genesis controllers are dead simple to interface with (wire=button). taqueso posted:How do you structure your tests? I'd like to be able to have tests for each module (and tests for the top-level). Should I have a top-level testbench that instantiates a bunch of per-module tests and clocks each test module in turn? I guess they could all be in parallel... taqueso posted:Honestly, I am pretty surprised how bad testing is for HDL. TDD/agile/unit testing is pretty huge in normal software development. I never had anything complex enough to require that large of a testing suite until I was in a professional environment. It shouldn't be too hard to make a simple wrapper around icarus though. Are there any SW test suites generic enough to take a cmd line and conditions for pass/fail?
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Sep 20, 2012 21:05
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JawnV6 posted:Yeah and HW dev is accessible to some vanishingly small % of people that SW dev is. The tools follow. quote:I never had anything complex enough to require that large of a testing suite until I was in a professional environment. It shouldn't be too hard to make a simple wrapper around icarus though. Are there any SW test suites generic enough to take a cmd line and conditions for pass/fail? I'm sure there are, or one could be made pretty easily. My thought there was to get SystemVerilog support, but no open source tools support SV as far as I can tell. I'm just trying to be a good boy and make my design have a nice self-checking test suite that could be partially reused for my next project. (Previously I have only used the look-at-the-waveforms-manually method of testing) I got Advanced FPGA Design by Steve Kilts yesterday and it has a chapter on test suite design and organization that looks pretty good. I am going to try and implement that. BTW, this book seems to have a lot of good info in it, but I have only skimmed so far.
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Sep 20, 2012 21:53
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CompEng PhD student checking in here. I think I might start on a project to add SystemVerilog support to the open source VTR (Verilog-to-Routing) toolchain. Yay! I may need to implement some new CAD algorithms, and want to push some of my own SV designs through it as benchmarks, without having to dumb down and convert it all to Verilog 1995 (the port naming syntax is so goddamn arcane...ugh)
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Sep 21, 2012 08:07
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Yes, do that, please. 
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Sep 21, 2012 20:14
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PDP-1 posted:And no, no Verilog/HDL experience whatsoever - this is my attempt to learn the basics from the ground up. I do have an EE background and some programming experience so hopefully that will provide a reasonable base to build from. The Altera DE1 and DE2 boards are pretty nice. The book "Embedded SoPC Design with Nios II Processor and Verilog Examples" is based on DE1 if you want a tutorial-style intro. There's also a VHDL version if that's your thing.
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Sep 24, 2012 23:44
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