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Poopernickel posted:Agreed that a page-swapping design doesn't scale well when you have more than two pages - in that case, your approach is the one to use for sure. With exactly two pages, however, the logic requirements are lower because the synthesizer doesn't need to implement a mux on each input and output bit. You probably get the muxes and logic for free if you're implementing it any modern, reasonable FPGA. If you're using registers, you're consuming a slice and its LUTs regardless if you use them or not, due to the control sets and routing resources. This whole discussion is exactly why whenever someone at work does something silly, I always, always, always ask them to draw out the schematic of what they're doing. If you can't figure out how to do roughly what you want with gates and FFs, you shouldn't be doing it. Even if you do know how to implement it with logic and gates, you should still try to have an understanding of your specific part to make sure that the synthesizer wont do something dumb. Remember that VHDL and Verilog are Hardware Description Languages - not magic, and you certainly don't write "programs" with them.
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Oct 18, 2011 03:14
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Poopernickel posted:What exactly is magic about the example that I posted? That was more of a general comment, not directed at you specifically. Mainly for the XOR atrocity that was posted earlier. I do think double buffering for the game of life would be pretty ridiculous - each element is the result of its neighbors, so you just have N identical copies of the same 9 to 1 boolean function and you only need 1 FF per game tile. I suspect the bigger problem will be routing congestion more than logic or FF use. Or you could use a RAM and just iterate through each row in the game - it's basically a 3x3 kernel that's passed over the game tiles.
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Oct 18, 2011 08:00
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mnd posted:I don't have much time to comment on this right now, so I'll just drop this here as a placeholder for a future conversation: https://github.com/stacksmith/fpgasm That...doesn't make any sense. In either VHDL or Verilog you can instantiate any primitive you want, and hook it up however you want. It's rare with slice/fabric elements though, because that tends to be one of those "if you have to ask, you're not qualified to use it" situations. And it becomes a migration nightmare when you want to move to a different device. It looks like a (rather poor) solution in search of a problem.
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Mar 30, 2013 06:43
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