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About to purchase an Altera DE0 nano board. Am I getting myself into trouble? I know nothing about FPGA and hardware design and I don't really understand HDLs. Also what's a good book on hardware design + vhdl/verilog? Preferably something that doesn't shy away from the math.
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# ¿ Mar 16, 2013 00:43 |
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# ¿ Apr 27, 2024 15:46 |
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Dolex posted:Get a spartan S3 (http://www.xilinx.com/products/boards/s3_sk_promo.htm) and this book http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/ Those boards are also $200. The de0 is like $90. Thanks for the book suggestion--even though it says xilinx it seems that most of it will transfer to altera with no real issues.
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# ¿ Mar 17, 2013 16:42 |
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movax posted:The absolutely cheapest way to get started in my opinion is the TI MSP430 LaunchPad. For the price of a Starbucks thingy, you get the programmer/debugger, the chip, loving everything. Ti ships them for free but it takes a while. Really nice hardware and a closer to metal feel than arduino
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# ¿ May 22, 2013 17:44 |
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JawnV6 posted:Eh, I wouldn't get it just for that. It's all "open" in some sense, but re-flashing the FPGA didn't seem like a high priority to make accessible. What's wrong with bluespec?
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# ¿ Jun 3, 2013 21:39 |
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Rescue Toaster posted:I would at least take a look at FRAM. There's a few different manufacturers, and it's more mature. I have no idea what the MRAM cost is, but FRAM can get fairly cheap in reels of 1500 for such a specialized chip. TI makes an MSP430 with some FRAM embedded on it but it's ~64KB tops
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# ¿ Jun 16, 2013 15:36 |
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JawnV6 posted:RTOS literally exist to provide real-time guarantees. It's half of the name. They offer easy hooks for writing ISR's and enforcing guarantees between them. I really don't know which ones you've worked with, but if you think they somehow enforce dynamic memory or a stack frame I'm not sure what to say. Most of them compile down to a static system you can inspect without much trouble if you've got that much skepticism about it. Stupid question: if you need hard realtime guarantees why go with an rtos on a uc over an fpga where you implement your algorithm in logic? Cost, complexity, validation? I think there are some fpga with hard procs embedded too for convenience.
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# ¿ Sep 7, 2013 08:59 |
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I found hdl to be superficially like writing frp code but I only made LEDs blink so I don't know how generalizable that is Fwiw conal Elliot, the arrowized frp guy now does work for an fpga company and arrows are very good at describing frp so maybe there's something useful there
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# ¿ Dec 5, 2013 23:44 |
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Spatial posted:Continuing this discussion. Even if you do t use forth look at how forth was built to get compact code
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# ¿ Jul 10, 2014 00:22 |
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No Gravitas posted:This is probably really loving stupid, but what the hell! sqlite
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# ¿ Jul 15, 2014 15:50 |
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No Gravitas posted:Thanks, but I just managed to make it all fit. More recalculating in post, but it works out now! OK so the standard trick (what SQL server/vertica do, at a high level) to doing this is to store it column oriented and then if you can run differences for as long as possible to reduce magnitude, then compress that with something like eg lzma/lz4
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# ¿ Jul 22, 2014 12:13 |
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JawnV6 posted:I'm selecting a protocol for an embedded sensing device to package up readings and deliver them to the cloud. The embedded side is a m4 in C, nothin' fancy like a file system. The cloud is python, java, or scala. The options I'm considering, along with my windbag opinions: protobuf is pretty rock solid. for other fun binary encoding times, consider avro, thrift or bond!
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# ¿ Sep 28, 2015 19:57 |
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travelling wave posted:Does anyone know why people define bit flags like this: you could then use an enum with autoincrement code:
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# ¿ Nov 29, 2015 14:08 |
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reading posted:Has anyone here worked with the Altera Cyclone V development board, the DE0-nano-SoC? yeah i gave up when quartus shat the bed 4 times in an hour if the only thing intel does w/ altera is make good fpga tools it'll be amazing
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# ¿ Dec 29, 2015 23:19 |
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Use Netfpga
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# ¿ Apr 7, 2016 09:49 |
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Stick your iot poo poo in electrical gangboxes. Easy to service and any electrician can add or remove them.
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# ¿ Jan 26, 2017 21:22 |
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csammis posted:Yeah, I wasn't thinking about the voltage drop over house-length runs Further advantages of gangboxes: you can mains to them and put in a cute little power supply. Don't tell your home insurer!!!!
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# ¿ Jan 26, 2017 21:23 |
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Alternatively run Ethernet and a 48vdc PoE switch
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# ¿ Jan 27, 2017 12:33 |
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JawnV6 posted:This is the one argument that I sorta believe, and that wavers day to day. The folks I know who are super into RISC-V are all carrying axes to grind, and they do that bitcoin thing where criticism from nearby-field experts are brushed off as "so make ur own orthogonal extensions " Nvidia is using it on GPUs as a watchdog micro Tbh it will likely compete more with xtensa and arc than arm unless apple decodes to stop paying for an arm license. Maybe it'll kill off some softcores on FPGA. The hifive1 mcu is neat but niche. Isa just doesn't matter that much when the code is high level. Also, Arm ip libraries are just more complete and developed. Malcolm XML fucked around with this message at 19:24 on Nov 9, 2017 |
# ¿ Nov 9, 2017 19:22 |
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JawnV6 posted:I dug around, the info's out there. Back when ex-coworkers were trying to recruit me for the thing it was hush-hush, but I was thinking of Dave Ditzel. It's basically a ME equivalent. it runs a bunch of "security" code and handles some DRM stuff too. The designer gave a talk about it https://www.youtube.com/watch?v=gg1lISJfJI0
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# ¿ Nov 9, 2017 23:57 |
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# ¿ Apr 27, 2024 15:46 |
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JawnV6 posted:Just set up the first scatter target as the end chain descriptor and have the DMA engine reprogram itself That's devious as heck
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# ¿ Nov 23, 2017 02:36 |