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I bought a tm4c launchpad board last night. 20 bucks and a cortex m4 and a zillion peripherals n poo poo
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Nov 27, 2014 02:54
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at my last job I got the go ahead to get a Freescale k60 going from scratch with a minimal tool chain, so I could learn I took the k60 programming reference and arm-none-eabi-gcc and made my own linker script and startup code that did things like initialize static variables and set up the multipurpose clock generator and stuff it's a good learning experience that teaches you why C is kind of a mess. when you are writing code you have to think about the hardware, the linker, the syntax, and your own code domain, standard libraries that may or may not actually be doing what you think I did a minimal amount of googling to force myself to really learn how to find answers for my weird questions 10/10 would recommend, I am now a mild embedded wizard
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Nov 27, 2014 03:11
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in my dumb opinion it's okay to waste cycles on simple applications in projects that don't need to scale or multi task much. get something done. optimize when it's time. structure your code base well so you can refactor your inefficiencies later
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Nov 27, 2014 03:17
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Mido posted:in my dumb opinion it's okay to waste cycles on simple applications in projects that don't need to scale or multi task much. get something done. optimize when it's time. structure your code base well so you can refactor your inefficiencies later Epic thissery. The field owns though when you find yourself optimizing stack usage to save individual bytes because it means writing out to flash slightly less frequently and now you can meet or exceed your power requirements etc etc. Desktop software is like you're an artist with an arbitrarily large canvass and you have so much freedom and room for activities that your constraints wind up largely self imposed but on a lil microcontroller it's like you have the back of a postcard to get as much done as possible Idk I'm bad at analogies good night yospos
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Nov 27, 2014 03:47
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I messed around with FPGAs a little in college and thought they were really cool and I want to get back into them. Can anyone recommend a decent breadboard?
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Nov 27, 2014 04:03
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I watched highly skilled engineers lose their loving minds over optimizing the gently caress out of things we didn't even really need I just wrote a huge rambling essay about some architecture horrors I lived through during my time in embedded but decided to summarize it as follows "if you have too many things going on for a cooperatively multi tasked series of services to work reliably, you should drop an actual RTOS on there and move on. do not make your own."
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Nov 27, 2014 04:18
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Locker Room Zubaz posted:I messed around with FPGAs a little in college and thought they were really cool and I want to get back into them. Can anyone recommend a decent breadboard? Yeah but only if by decent you mean expensive and horribly complex Or at least expensive Actually I'm not sure if it's expensive but the igloo nano dev kit is pretty cute and painless. Digilent (I think?) makes some decent educational stuff too iirc
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Nov 27, 2014 04:29
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Mido posted:I watched highly skilled engineers lose their loving minds over optimizing the gently caress out of things we didn't even really need i read this and i think: faaaaaaart just run x86 on it and be the fastest because that is how the real world works.
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Nov 27, 2014 04:38
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kwinkles posted:i read this and i think: faaaaaaart I was talking about software project and dependency structuring not the on die architecture 
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Nov 27, 2014 04:41
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kwinkles posted:i read this and i think: faaaaaaart RIP power budget
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Nov 27, 2014 04:47
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are there x86 core MCUs that have the same kind of features as say a Kinetis K60 series? I've never looked the Kinetis is a monster with a fuckload of peripherals and gating options for power consumption and a pretty good cross bar thing that reduces contention when peripherals are doing DMA
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Nov 27, 2014 04:50
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Bloody posted:Yeah but only if by decent you mean expensive and horribly complex igloo nano is good, i'm using that dev board to prototype for real stuff digilent makes good altera dev boards, the bemicro sdk is a good dev board as well that just plugs right into a usb plug, has a cyclone iv on it for xilinx spartan 6s are the little ones, a kickstarter just finished for the miniSpartan which might be OK. the zynq is pretty legit, you can get get the avnet zedboard and make your own custom linux machine which is legit all of those options are around like $100-$200 i think
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Nov 27, 2014 05:44
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Mido posted:are there x86 core MCUs that have the same kind of features as say a Kinetis K60 series? I've never looked the embedded stuff (atom, etc) comes closest, but even then, iirc its just multiple dies inside and the pch has all the peripherals -- x86 cores interface to any/all peripherals over pcie or dmi one of the intel guys in the thread will probably correct me on that
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Nov 27, 2014 05:46
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movax posted:the embedded stuff (atom, etc) comes closest, but even then, iirc its just multiple dies inside and the pch has all the peripherals -- x86 cores interface to any/all peripherals over pcie or dmi i haven't really played around with it too much but i think the quark will have the old FSB architecture and the edison board that has silvermont cores will be the faster and lower power option. i know silvermont has the same IDI interface to the system agent that the big cores have now, and most of the stuff that is on-die will be hanging right off the system agent with IOSF or the intel memory requestor busses. i know the galileo board has some of the GPIOs hanging off the north complex and some hanging off the south complex because i see the function for fastGpioDigigalRead that I am using calls two functions with NC or SC in the name depending on which pin I am writing to, and the NC and SC appear to be on-die in the quark because the pins go right from the quark to a level shifter. i dont really know what is going on on-die tho.
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Nov 27, 2014 17:30
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Bloody posted:I bought a tm4c launchpad board last night. 20 bucks and a cortex m4 and a zillion peripherals n poo poo I have ordered this board. will post trip report.
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Nov 27, 2014 22:44
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~*mY dEsK*~ 
a_pineapple fucked around with this message at 00:16 on Nov 28, 2014 |
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Nov 28, 2014 00:14
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is dat sum teensy3? good poo poo op
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Nov 28, 2014 00:16
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I'm the through hole clown devices
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Nov 28, 2014 00:31
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there are still people using something other than Cortex-M chips for something that doesn't have to be ultra low power smdh (i'm one of them, this project uses an STM8 because it needs to be dirt loving cheap but i mean apart from the IAR license wiping out the money we saved on the BOM cost several times over because this is a hilariously low volume product you could do worse) poo poo i mean you can get actual application processor SoCs for like $10 these days if you're man enough to lay out some DDR lines  i write some fairly ownage firmware but i've never designed a PCB before and i'm not sure i'd want to start in a situation where my job depended on me not loving it up  also the other day i thought "hm, connecting AA batteries in series sums the voltage, right? ok just making sure" so yeah maybe i'm not the best man for that particular job
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Nov 28, 2014 01:24
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teensy3? 
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Nov 28, 2014 01:24
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Mr Dog posted:there are still people using something other than Cortex-M chips for something that doesn't have to be ultra low power Aww yiss ddr termination
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Nov 28, 2014 01:55
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Sagebrush posted:is dat sum teensy3? good poo poo op Mr Dog posted:teensy3? Werthog 95 posted:lol when hobbyists roll in and tell you "avr supremacy" just because that's what arduinos use
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Nov 28, 2014 02:07
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last thing i used my arduino for was hooking this thing up to my computer then i couldn't think of anything worthwhile to do with it so now it sits there with wires hanging out its rear end
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Nov 28, 2014 02:08
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teensy 3 is a cortex-m4 dumbass
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Nov 28, 2014 02:09
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one with an amazingly lovely register layout that doesn't even seem to come with CMSIS headers, yes i'm the big-endian IP cores on a little-endian processor
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Nov 28, 2014 03:03
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im a dumb hobbyist but microcontroller poo poo is fun as heck i wired up a 4 digit 7 segment display and the first iteration i kept having some of the segments were dimmer than the others and when it finally clicked what i was doing wrong and how to resolve it i was all like  just having to think about microseconds of delay and poo poo like that is a really fun exercise even if 'display 4 digits at a time' is a solved problem
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Nov 28, 2014 03:11
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maniacdevnull posted:im a dumb hobbyist but microcontroller poo poo is fun as heck it can definitely be fun and it's very satisfying when you figure out that what you were doing wrong in the programming sequence, yeah. this must be what it feels like to work in post silicon verification except there's no money riding on me figuring out how to make this silly display work.
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Dec 1, 2014 00:39
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Bloody posted:good poo poo trip report: the ladies loved it
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Dec 1, 2014 00:40
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how many gates would an FPGA reasonably need to support to emulate a Lisp Machine CPU? like first-gen, the CADR/Lambda/TI Explorer
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Dec 1, 2014 03:48
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for baby's first electronics project I'm going to be wiring up my apartment buzzer to internet via raspberry pi and then ideally going to an ESP8266 because I hear that it's the cool thing to do these days
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Dec 1, 2014 04:04
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Sagebrush posted:teensy 3 is a cortex-m4 dumbass lol, ok, sure
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Dec 1, 2014 04:07
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Jimmy Carter posted:for baby's first electronics project I'm going to be wiring up my apartment buzzer to internet via raspberry pi and then ideally going to an ESP8266 because I hear that it's the cool thing to do these days hook it up to one of these so you squirt whenever you have visitors. 
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Dec 1, 2014 04:09
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movax posted:personally i would de-feature msp430s out of existence, i hate the loving things (mostly the fram family) and documentation can you give me a litany of complaints about them, the fr57xx is one of the chips in consideration for a design i'll be working on in a couple of months
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Dec 1, 2014 05:09
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Their architecture is bad and their mips per mw or whatever power metric you want is bad
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Dec 1, 2014 05:24
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Mr Dog posted:there are still people using something other than Cortex-M chips for something that doesn't have to be ultra low power
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Dec 1, 2014 06:09
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kwinkles posted:it can definitely be fun and it's very satisfying when you figure out that what you were doing wrong in the programming sequence, yeah. Silicon verification loving sucks horse dong.
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Dec 1, 2014 06:14
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Blotto Skorzany posted:can you give me a litany of complaints about them, the fr57xx is one of the chips in consideration for a design i'll be working on in a couple of months sw dude complaints: - lovely toolchain (ccs, mspgcc, gcc-msp430), iar wasn't considered because it's windows only - lovely docs - weird-rear end isa (certain operations very expensive like bit shifts  ) also forget about doing intensive mathhw (my) complaints: - lovely docs - weird pinouts sometimes - fr5969 has funky errata relating to leakage currents on certain pins - weird rear end fram memory controller timings that changed from stepping to stepping - took them six steppings to get release silicon out which is mildly terrifying - you will need a reset supervisor or otherwise clean reset source, code will corrupt in brownout conditions (the SVS module on the frxxxx parts for some reason is slightly different than other msps) the fr57xx series is older and their first go at the whole fram thing; new designs i'd check out the fr5989, if you can get it (i bought the first batches out of the factory) like i said though, i'll give them props for the absurdly low power consumption and fram reliability
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Dec 1, 2014 07:00
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eschaton posted:how many gates would an FPGA reasonably need to support to emulate a Lisp Machine CPU? the low-end parts from altera or xilinx should be able to do it easy (spartan-6, artix-7, cyclone iv or cyclone v) -- there was a recent kickstarter for a spartan6 devboard which would work, or check out digilent's de-0 or de-1 i didn't see what cpu the machines used on wiki, but for 1980s vintage, i don't think you're running out of gates anytime soon.
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Dec 1, 2014 07:02
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kwinkles posted:i haven't really played around with it too much but i think the quark will have the old FSB architecture and the edison board that has silvermont cores will be the faster and lower power option. i know silvermont has the same IDI interface to the system agent that the big cores have now, and most of the stuff that is on-die will be hanging right off the system agent with IOSF or the intel memory requestor busses. yeah gailelo (whichever one came first) is the og pentium cores on a newer process. do either of those new boards expose gpios via io space? seems like a no-brainer place to put some i/o for x86 so you can just outb() inb() all day long just stay away from outb(0xf5, 0xb2) (probably not a problem on those guys though)
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Dec 1, 2014 07:05
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movax posted:the low-end parts from altera or xilinx should be able to do it easy (spartan-6, artix-7, cyclone iv or cyclone v) -- there was a recent kickstarter for a spartan6 devboard which would work, or check out digilent's de-0 or de-1 the Lisp Machines used custom CPUs specifically designed for ease of Lisp implementation. (which isn't the same as "running Lisp in hardware" as some people claim.) they also had writable microcode, so the lowest-level operations could be made as fast as possible the CADR emulator and Explorer emulator codebases provide C implementations that could probably be used to author some VHDL with effort, the main thing I'm wondering is if I'd get partway through and find out that lol, my Spartan 6 won't have anywhere near enough gates I suppose since the original systems were literally a few square feet of 7400-series chips I should be able to estimate the gate count from that (hell, even just based on physical density)
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Dec 1, 2014 07:16
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