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So, combined CCX and EMIB latencies are going to be hell of an annoying thing? The idea of a 16C/32T CPU tickles my fancy, if it's sub-1000bux.
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May 17, 2017 16:58
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| # ¿ May 2, 2024 06:58 |
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Eh, so long the console generations don't last like 10 years again and PC gaming is the victim again by things being held back due to multiplatform poo poo. I mean, on the CPU front, things like IPC improvements have been slowing down for a while now, still current quadcores beat the consoles silly, and trend is going towards more than four cores, via Ryzen and also Intel's Coffee Lake. On the GPU side, dies are getting bigger and bigger and continue bring significant improvements due to easy parallelization.
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May 21, 2017 11:25
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Interesting. If the frequencies shown there is what the CPU ran at, instead of nominal while they were actually turboing, bumping the Whitehaven to 4GHz would mean near perfect linear scaling. Which seems doubtful, unless they've improved the interconnect speeds. Which means that the 8C's handicap makes the difference for the scaling to appear linear. So anyway, are there any significant teething issues with Ryzen, that haven't been fixed yet with BIOS updates?
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May 21, 2017 19:42
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I did the GPU passthrough stuff a while ago. Worked just fine. However I refused to run the Linux desktop on a secondary poo poo GPU, so I ran either Xorg or Windows on my fat GPU (games and all). Given all the sing and dance, I might as well just have dual booted.
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May 22, 2017 01:04
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So without availability date, I suppose there won't be early samples going to reviewers any time soon?sauer kraut posted:Good god Threadripper is the size of an old school hard drive
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May 31, 2017 11:49
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 If that 16C price is true, I don't think I'll give too much of a poo poo about interconnect latencies. Gaming makes up only a fraction of all workloads.
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Jun 2, 2017 10:38
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Oh dear:  Every new news item keeps making me flipflop between AMD and Intel. --edit: I love how that dumb spreadsheet linked in the Phoronix article asks for mainboard but not which CPU version. Might as well turn out to be an issue with binning, AMD being a little too optimistic about the higher end models or some poo poo like that. Combat Pretzel fucked around with this message at 21:24 on Jun 4, 2017 |
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Jun 4, 2017 21:22
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Anime Schoolgirl posted:similar problems happened with sandy bridge and didn't really even get fixed until ivy bridge. especially with the P67
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Jun 9, 2017 12:36
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repiv posted:In true AMD fashion, they've released the Zen software optimization guide... over 3 months after Zen launched.
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Jun 15, 2017 00:08
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eames posted:heise.de reports that Skylake-SP (and Skylake-X) uses a mesh (like the Xeon Phi) instead of a ringbus
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Jun 15, 2017 19:31
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I suppose the physical layout of the LCC chips is 4x3, given that the top end part has 12 cores? --edit: Nope, 6x2. --edit: I wonder if the LCC part actually has a mesh or still uses the ringbus.
Combat Pretzel fucked around with this message at 19:43 on Jun 15, 2017 |
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Jun 15, 2017 19:40
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Paul MaudDib posted:I've been redesigning my fileserver, right now I am thinking of having a NAS with ZFS and ECC and an infiniband connection to an actual application server with good performance (perhaps Threadripper). It's a mITX or mATX case with 8 bays and I want another drive for boot/L2ARC cache (M.2 is nice).
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Jun 17, 2017 10:29
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Yea, but it only fetches into primary ARC. L2ARC doesn't retain streaming data by default. Seems to be some algorithm that caches blocks that look popular, so that start of IO gets served out of L2ARC to give the disks time to start streaming. The relevant tunable is vfs.zfs.l2arc_noprefetch, set to 0. --edit: Wrong thread for this, anyway.
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Jun 17, 2017 11:44
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Mr Shiny Pants posted:Everyone has sucky products once in awhile. I just hope AMD gets theirs sorted quick. I want a Threadripper ASAP.
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Jun 17, 2017 21:49
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Hope that B2 stepping lands in the Threadripper. Is two months to release enough time to get dies manufactured and packaged into the MCM?
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Jun 18, 2017 19:45
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Meh. Regardless of that, ECC memory, the fastest I've found is from Crucial, being DDR4-2666. However CAS is 19, not a fan of that. I wonder if the memory chips are binned well enough to be able to drive it down a lot, say to 15-16.
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Jun 18, 2017 21:17
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Zen+ is scheduled for when? Beginning 2018? The B2 stepping ain't it, right?
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Jun 20, 2017 15:38
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eames posted:so there's hope that Threadripper will be B2 and fix annoying errata like the NPT GPU pass-through performance bug. Question is whether Threadripper also gets the B2 stepping already, or whether they're running down their B1 stock on it first. I suppose it'd be an idea to monitor whether B2 Ryzens are showing up soon.
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Jun 22, 2017 10:38
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At least AM4 doesn't fry your CPU, whenever you intent to use that weird upgrade path Intel thought up.
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Jun 22, 2017 11:11
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Desuwa posted:Searching for NPT and ryzen in the VFIO subreddit will turn up some discussion over people attempting to manage it. The short of it is that leaving NPT enabled will ruin GPU performance but disabling it will ruin CPU performance.
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Jun 23, 2017 09:08
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ZBrush is a general shitshow. I mean, it's UI looks like it's from a 90's MOD tracker running on DOS.
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Jun 24, 2017 11:33
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Paul MaudDib posted:Assuming they can fix the problems with leaking in the first-gen kits, EKWB does have a really nice setup where it's basically an AIO out of the box and you can buy "prefilled" GPU blocks that attach using quick disconnects. That seems pretty good to me.
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Jun 27, 2017 21:09
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A while ago I've seen a video of some Linux dude testing it and forcing errors by loving with RAM voltages. It actually reported single bit errors under Linux. And caused a kernel panic on worse errors. I figure it'll do the same in Windows, too. Also, they need finally to officially announce/reveal Threadripper.
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Jun 29, 2017 19:46
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You actually need to wait for at least three months after the reveal to see actual effects. People need to save money and then buy poo poo. And OEMs need to sell computers with Ryzen.
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Jul 2, 2017 23:00
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Been loosely digging into running Ryzen at 4GHz. Kind of reads all like a shitshow. I suppose I should sit it out for Zen+ or Zen 2 (or rather, their Threadripper variants), whatever the gently caress was supposed to go up to 4.5GHz.
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Jul 4, 2017 20:12
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Visually, my most ideal case would be an S340 without windowed panel. A black slab with a simple optional color accent. But it's a sing and dance with the NZXT support to get a solid replacement side panel.
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Jul 5, 2017 12:04
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So there's actually no Threadripper rocking it like it's 1998X?
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Jul 6, 2017 22:06
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Geekbench seems ridiculously useless. I've been looking up my current CPU on it to compare it to these supposed TR 1950X results, and within the results, there's huge disparities, like a presumably stock clocked 5820K returning higher results than severely overclocked ones. (Or at least the app seems to be royally stupid about recording clock speeds.)
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Jul 8, 2017 16:56
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So about MCM latencies of TR/EPYC, I suppose it would have been better to have a memory controller as separate entity on the IF and have the CCX groups be autonomous?
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Jul 9, 2017 12:45
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From all I've read, it sounds like cross-CCX L3 cache accesses are the royal pain in the rear end, and probably one cause for funny latencies. Having a memory controller, maybe with some of its own cache, as separate entity on the IF, and disabling cross-CCX L3 accesses, things might be less bad? Just sounds sorta idiotic to access L3 cache on another CCX at memory speeds. Might as well just hit the memory directly. I'm also just armchairing. Cygni posted:If NUMA aware OS didn't exist, that might be worth it. But with NUMA, and most calls being the first two options, the current solution on Epyc is probably much more efficient. I suppose it doesn't matter so much for the current bunch of Ryzens, since as you say, the bandwidth is high between a pair of CCXs, but I'm eyeing at TR, and it sounds like I don't want it, if gaming is part of the workload for it. Combat Pretzel fucked around with this message at 00:19 on Jul 10, 2017 |
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Jul 10, 2017 00:14
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Oh, I have things to occupy all 16 cores once a while. What I'm more concerned about is when there will be situations when NUMA is going to be a problem, i.e. mismatch between core a thread is running on and where memory allocations are. At a certain point depending on memory pressure, allocations will start to cross NUMA memory regions. If the IF bandwidth between CCX pairs is indeed so much worse as speculated, this is going to be noticeable in some form. On the other hand, if IF is 32 bytes wide and can run an PCIe speeds, as said a couple of posts above, why the hell are there even bandwidth issues that depend on RAM speed? Combat Pretzel fucked around with this message at 11:23 on Jul 10, 2017 |
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Jul 10, 2017 11:21
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So uh, if it's super high bandwidth, why does it get hosed over by the memory clock? Sounds like its data transfers are gated by the memory controller? If so, why?! I guess I kind of fail to see why it gets punished so hard versus Intel's ring bus.
Combat Pretzel fucked around with this message at 16:50 on Jul 10, 2017 |
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Jul 10, 2017 16:48
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wargames posted:Also Zen1 doesn't use Numa for CCX talk it uses a new scheduler that microsoft and AMD came up with to account for the slight higher CCX talk.
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Jul 10, 2017 18:18
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It's a single socket, but things look awfully like it being a Frankensocket (two smashed together). So yeah, NUMA.
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Jul 10, 2017 19:22
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If that's 4GHz boost, then I'm in. The IPC should be equivalent to my 4GHz Haswell-E, but I'd gain 10 cores and ECC.
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Jul 13, 2017 15:06
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eames posted:Four core 4 GHz boost seems realistic to me, double that of a 1800X and one core per Die.
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Jul 13, 2017 15:29
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Actually AI is a thing that can be easily parallelized. Each agent can be simulated on its own thread.
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Jul 13, 2017 20:58
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Better not be some bullshit changes introduced to make that Linux subsystem stuff work. Process creation and tear down is already heavy-handed as is in Windows.
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Jul 13, 2017 22:16
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On the other hand, depending on what you want to have running on your board, you might want to wait. That said, if the supposed 8C/16T TR clocks high enough, I might get tricked into upgrading the CPU eventually. Now a cheap TR waiting for a TR+ or TR2.eames posted:Zen+ may introduce its own infinity fabric multiplier so the interconnect runs faster with slow RAM. Intel's ringbus already does that and the knowledgeable folks at anandtech agree that there's no good reason why Zen doesn't, short of "AMD ran out of time for the Ryzen launch". Combat Pretzel fucked around with this message at 12:42 on Jul 15, 2017 |
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Jul 15, 2017 12:34
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| # ¿ May 2, 2024 06:58 |
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14nm+ for H1 2018 or what?
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Jul 19, 2017 23:38
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