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spasticColon posted:The Dreadnought class starship USS Threadripper. In other news, the newest of the Ryzen class super-dreadnaughts, the Joro Vara launched last week amid fanfare and celebrations at the Advanced Macro Devices shipyard in the Jitzu system. Reports suggest the ship is armed with an unbelievable 48 weapons cores, with a spinal mount Threadripper super-string destabilization cannon. All eyes look to the competing shipyard conglomerate INTEL-NVIDIA in the Pascal-Prescott star cluster for their response. Our hopes and prayers go with our brave fighting men on the front lines against the ArchFoe.
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May 14, 2017 22:20
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I'm just waiting for the APUs to have 16 or 32GB of HBM2 memory onboard and smoke the crap out of most of the discrete GPU systems out there. You can save a ton of cash by having everything on a system board the size of a postcard, and parley that into a thinner lighter product, or a product that's like 60% battery by volume. Actually, I'd be super interested in an AMD CPU in a laptop with 16-32GB of HBM2 even without the integrated graphics. I wonder if it would be possible to have off-socket HBM, or if the 8 shitzillion traces would cause it to fail miserably.
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May 24, 2017 02:49
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Drakhoran posted:According to Fuad Abazovic, one 4GB stack of HBM2 memory costs $80. 16GB ($320) on a laptop CPU is not going to happen until prices come down. As volume starts to ramp up, we'll probably see HBM2 go the way of flash memory, dropping ~30-50% year over year as speeds go up and capacity improves. Hell, I remember when 4gb of DDR2 cost $80, and HBM2 is literally 100x faster.
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May 24, 2017 20:34
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Kilson posted:Are those wooden fans (edit: casings)? I imagine it's some kind of stupid audiophile equipment Nah, those are Noctua fans, super quiet, good airflow, and all the case-window spergs think they're ugly as poo poo for some reason, but gently caress them. They're pretty popular to bundle with heatsinks that either don't come with a fan, or come with a really lovely one.
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May 29, 2017 17:06
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If they can get the infinity fabric fast enough and low enough latency, then it shouldn't be too much of an issue, as long as they address the NUMA issues and make sure that all the context switching costs are known/available to the OS. It would be a great way to salvage marginally performing chips, or chips that are super great except for that huge defect in core 3.
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May 31, 2017 00:26
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SwissArmyDruid posted:Ah, so THAT'S why Raja isn't standing in line for unemployment yet. The thing is that $500 chip with $150 in direct variable costs has a completely stupid amount of R&D associated to it, probably to the tune of $100-150, depending on projected volume. The margins on the chips isn't that great once you figure in all the other poo poo they need to do to get the the point where they can make one. FaustianQ posted:The HBCC memory controller AMD is talking about has me thinking, could AMD turn HBM2 into a nonvolatile storage medium, or even a PCIE Ramdisk? HBM is too expensive AND too fast to justify a PCIE ramdisk. A dual channel DDR4 memory controller attached to a PCIE bridge chip would saturate even a 16x PCIE 3.0 channel. Methylethylaldehyde fucked around with this message at 21:20 on Jun 2, 2017 |
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Jun 2, 2017 21:16
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SwissArmyDruid posted:Alright, I parted out a pair of identical machines for the two munchkins. Anyone mind casting an eye over and making sure I've not hosed anything up? https://pcpartpicker.com/list/G3bVQV I'd bump the ram to 16gb, just because 2x8 is way better than eventually getting 4x4.
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Jun 2, 2017 23:08
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Malcolm XML posted:Nah just create an ocp box and then the clouds will eat that poo poo up If they want to sell trays of chips to a single consumer, yeah the cloud providers are the way to go.
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Jun 4, 2017 20:06
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PerrineClostermann posted:So far, results aren't promising. Given the 6-8 month long lead times just getting a finished on the shelf design produced, if AMD played it close enough to their chest to catch Intel completely off guard, it wouldn't surprise me to see that this IS Intel's reaction, the only one they could really perform within a year.
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Jun 8, 2017 17:04
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SwissArmyDruid posted:...silicon, eames. Silicone Valley is in SoCal. Silicone valley is also a line of BBW and SSBBW inspired pocket pussies, though you'd need one of those JNCO pants from the 90s to actually fit it in a pocket. Edit: The marketing department is having issues coming up with a new name, the front runner is backpack bubble butt, but so far it hasn't gained much ground. Methylethylaldehyde fucked around with this message at 00:48 on Jun 15, 2017 |
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Jun 15, 2017 00:44
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wargames posted:Probably was this works and we can put it out without delays or costing us too much just make it happen. That and an async clockgen for it would complicate the poo poo out of a lot of things, complications they desperately were trying to avoid at all costs. Now that Zen1 is the poo poo, they can work on teasing out all that performance they left on the table, you know, the stuff in the big box labeled 'untested, do not touch'.
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Jul 10, 2017 21:14
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Cygni posted:The best case (and most likely) is that Threadripper equals an 1800X in gaming for twice the price. The worst case is that NUMA doesnt work well at the OS level or games just don't play nice with it, and it ends up actually slower than an 1800X clock for clock. I don't think thats likely at all, but we will see soon. Or any gamer that wants to lock the twitch encoding/chatbot to 2 cores and let the game and OS have the other 6-14
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Jul 25, 2017 03:52
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HalloKitty posted:See, that's what I assumed, so none of this makes sense, unless they're failed dies put in place just to keep the heatspreader level or something weird. Single socket style, single interposer/package style, single soldering setup to work the kinks out of, all for the cost of whatever wasted/dead dies. From a process simplification standpoint, it could work.
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Jul 27, 2017 20:35
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isndl posted:Unfortunate? You know Asrock engineers live for this poo poo, they would have gone insane years ago otherwise. Yeah, but the Asrock engineers are well past the 'he only does it because he loves me' stage of battered wife syndrome and down the rabbit hole of 'it hurts so good daddy' hardcore masochism. Damned if the end result won't be a mini-itx Epyc system.
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Jul 28, 2017 08:10
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PerrineClostermann posted:Perhaps we'll see a new, inventive form of rebate for manufacturers? Yeah, but gone are the days of bribing Dell, HP, and E-Machines to lock in 90% of the market. CPU sales are gonna be on the Cloud providers and backend, and because of them much more likely to be subject to increased scrutiny by people willing and able to call them on their bullshit. Also after the EU Intel anti-trust ruling, they're going to be at least a little bit more circumspect than 'never use our competitor ever and get 20% off our chips'.
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Aug 15, 2017 06:34
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PerrineClostermann posted:I dunno, Intel seems to be able to appeal that ruling indefinitely. Yeah, but 'we literally did the exact same thing you're fining us for again' can curtail the appeal some. Not sure how the EU appeals system works, but that would be the kind of flagrant disregard for the law that would get a judge to issue penalties.
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Aug 15, 2017 06:48
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Seamonster posted:I'd like to say its as much the density afforded by 14nm and smaller going forward that allows for all this fancy MCM stuff, especially for GPUs because at 28nm, even if scaling efficient, fuuuuckk that package size. It's also so you can make designs that would be completely unfeasible without MCM. An Epyc with a 16 core Ryzen refresh as the individual die would probably end up pushing the boundaries of the reticle size on modern commercial equipment, same as how the Fury cards were bumping right against the total possible die size restriction on the old 28nm process. I picture a graphics card that consists of 2 or 4 cores that talk to a single stack of HBM 2 a piece, so you can spread the thermal load out across a larger area and use substantially cheaper masks, with a much higher yield, because you're making 4 parts that are 160mm^2 vs. one part that's 550mm^2.
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Aug 23, 2017 14:05
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FaustianQ posted:JD.com and Tencent are onboard with EPYC, and AMD has Sugon and Lenovo now for additional OEMs. That's loving huge http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-newsArticle&ID=2295144 Pretty much, 10% of Intel's server and compute gross revenues is a fuckhuge quantity of money for AMD.
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Aug 24, 2017 04:55
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I still don't understand why they don't offer a 'overclocker's edition' that has the old school shim+bare die.
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Oct 6, 2017 21:02
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FaustianQ posted:LMBO, I guess this will prove what was holding RTG back in about...2-3 years? That's the usual bring up time for a GPU uarch. Like, the earliest this has any impact is January-March 2019, and that's with basically the current gen uarch Intel has. if they're doing a clean sheet design with the fab advantage Intel taditionally has, and a good working idea of what needs doing with a new Vulkan/DX12 design, I could see it being pretty compelling. Most likely a dumpster fire, but still.
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Nov 9, 2017 00:39
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JockstrapManthrust posted:My understanding is, as it’s currently using a ratio of the dram clock, that giving it its own clock domain and ratio system would fix this as a low hanging fruit type optimisation. So there is every chance that this is fixed in zen+. Pretty much, it's something you do all the time in FPGA design optimizations, setting different frequency domains, buffering inputs and pipelining all work quite well at getting otherwise async parts to all play nice with eachother.
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Nov 22, 2017 01:38
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Fauxtool posted:im doing a new build with a 1600 and a gigabyte x370 k5 that i got a screaming deal on at microcenter. 3200ish is the magical spot where it slows down substantially, the difference between 3200 and 3400 or 3600 absolutely ins't worth the stupid high cost of those kits.
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Nov 23, 2017 08:04
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Paul MaudDib posted:There are polysilicon fuses that control core configuration and whether various features are enabled. So to make an R3 you take the basic 8C16T processor and blow the fuses that turn off 4 of the cores and the hyperthreading. Sometimes there are mistakes or omissions in the configuration, for example this is how you get 8C8T R3s and such. Intel's E5-1600 processor line also happened to use virtually the same feature fuse configuration as the consumer i7s and so they actually had the multiplier unlocked and were overclockable up to the v3 generation. I'd be laughing so hard if in order to guarantee that the fuses don't accidentally gently caress your chip up, they overenginner them so hard that occasionally they don't respond to the 'blow me up please' command, which is why we're seeing occasional R3s with 8 cores or whatever.
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Nov 26, 2017 14:23
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So sad news, despite having it as an option in the BIOS, having the IOMMU setting enabled causes Server 2016 to poo poo itself and refuse to load on basially every x399 motherboard. Which means no discrete device passthrough, and no shiny new tape drive directly attached to the file server VM  Hopefully they patch it in another few months, otherwise I'm gonna be kinda sad.
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Nov 29, 2017 12:24
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Combat Pretzel posted:Yes, the IF runs at half the memory bus speed. But it's like 4 times as wide (256 bit vs 64 bit memory bus). There's gotta be some buffering already. IF is also a packet based setup, similar to PCI-E, so running them completely async shouldn't be an issue fundamentally, you still have flow control and congestion management on the fabric, you just run them both as fast as they can, and deal with buffer over and underruns on the IF crossbar like you would any other memory tech. It's certainly hideously more complex than that, but fundamentally nothing about IF needs to be tied to a specific clock domain.
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Dec 11, 2017 18:50
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To be fair, Semiaccurate seems to have a huge hateboner for Intel, no idea what they did to piss in his cheerios back in the day, but a lot of the articles have a pretty obvious bias towards them.
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Dec 14, 2017 20:53
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I think a lot of it is that every chip they have is going into validated boards for partner sales through HP/Supermicro, etc.
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Dec 23, 2017 22:47
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fishmech posted:Well, it does need constant refreshing. What is the tREF and tRFC for a memory related scandal these days?
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Dec 31, 2017 22:15
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Anime Schoolgirl posted:samsung is already making 3200mhz dies but all of them are going straight into HPC and are $$$$$$custom orders I have a TR 1950x with 64GB (4x16GB) of Samsung B-die ECC RAM, and it works fine. Mem overclocked just fine, bumped it from 2400 to 2933 or so with a slight voltage bump. System sees that it's ECC and if I go full retard on the OC, you can see the system log start to rapidly poo poo itself with single bit ECC errors, so it works fine. Asrock X399 taichi, 1950x, the Liqtech TR4 360mm, and my usual pile of add-in cards. I'm not looking forward to a die shrink/refresh for my TR, but holy poo poo, getting an extra 400-700 Mhz and possibly 50% more cores would be amazing.
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Jan 9, 2018 06:16
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redeyes posted:dude is nuts, randomly taping off pads to narrow down the sense pin Wouldn't take more than 10 or so tries to narrow it down if you just cut in half each time. That said, if you can get a TR 1950x to work in a workstation Epyc motherboard that has unborked IOMMU and ECC support, I could see them being pretty kickass for certain kinds of simulation work, the kind where the sim doesn't scale well past about 16-24 cores, so having tons of Ghz to throw at it would work nicely.
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Jan 29, 2018 14:52
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Stanley Pain posted:IOMMU and ECC work properly with TR. Pretty sure the IOMMU problem was a known issue with KVM. Not really? Win 10 and Server 2012 won't boot if you have IOMMU enabled. I had to disable it to get it to do more than sit on the black loading screen. Perhaps they fixed it in recent BIOSes, I'll have to shut everything down and check again. ECC works great, and makes overclocking RAM super easy, since you can run the test while watching the system log for the ECC errors to report themselves.
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Jan 29, 2018 18:03
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Nono, I'm running Server 2016 as the hypervisor, and it really doesn't like it for some reason. Hyper-V is what work uses, and it's what I use because it works well enough for me, at least until now.
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Jan 29, 2018 19:19
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Stanley Pain posted:Ah, Yep, I just wanna be able to feed my SAS controller and tape deck directly through to the VM, instead of needing this hilarious round robin of tape drive to tape redirector to isci target to VM side thing. But we shall see.
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Jan 29, 2018 19:50
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Stanley Pain posted:How many TB of Linux ISOs are you backing up now? Currently? Like 50TB-ish? Edit: I'm lusting hard after the new LTO-8 tapes. 12TB per tape.
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Jan 29, 2018 20:09
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I snagged 8 x 10TB HDDs over black friday. 
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Trip Report: gently caress Windows Server 2016, and gently caress needing 1703 to get IOMMU to play nice with AMD. Server Core is the loving devil and god help anyone who has to use it outside of huge environments.
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Feb 3, 2018 04:44
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VostokProgram posted:But then I'd have a motherboard named "Fatal1ty" It's the reason I got the Taichi instead. Plus I'm saving my lunch money for some QDR infiniband off ebay if I find a good deal.
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Feb 5, 2018 22:06
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Anime Schoolgirl posted:the 2600x/2700x might actually come with a cooler this time? Through holes and Vias is what I read a while back, since it doesn't matter as much if they're a little ratty looking due to quantum electrodynamics and charge tunneling voodoo.
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Mar 8, 2018 02:15
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I read the thing looking for any actual CVEs and the entire thing looks like a hatchet job designed to scare institutional investors away from AMD. Lots of bright, pretty graphics and scary sounding phrases, but no proof of concepts, actual expoits, or anything more than 'if yuo load code in the ring 0 management engine, bad things could happen!!!11!'. Which, to be fair, is true, but also completely retarded to list as an exploit/risk.
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Mar 13, 2018 19:11
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Paul MaudDib posted:And yeah, this is basically exactly what people were worried about with the PSP. So much for AMD's security audits, if a two-bit outfit like this managed to drum up a whole bunch of breaks that doesn't really say much. Until they manage to find a "yeah, send a blank password strong to port 5675 on any vPro laptop to get root IME access" type remotely exploitable CVE, this is basically a 'yeah, patch your BIOS once it's out' kind of deal.
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Mar 14, 2018 07:13
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redeyes posted:Yeah thats a little odd now that you mention it. How about some of the new 6 core Intels to compare with.. Because the new 6/8/10 core chips use a mesh topography vs. ring, which can do interesting things to the inter-core latency.
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Mar 17, 2018 20:45
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