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riscv did it/ is doing it like it or not
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May 13, 2017 02:20
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I thought Intel's plan was to have Itanium be 128-bit so more data could be loaded into the registers from RAM, and you could do things like double the number of 64-bit multiplies in one clock cycle compared to 64-bit processors.
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May 13, 2017 02:32
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qkkl posted:I thought Intel's plan was to have Itanium be 128-bit so more data could be loaded into the registers from RAM, and you could do things like double the number of 64-bit multiplies in one clock cycle compared to 64-bit processors. most modern processors have 128-bit or larger vector registers that can do this, including x86_64
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May 13, 2017 03:00
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The Management posted:most modern processors have 128-bit or larger vector registers that can do this, including x86_64 yeah but the bus can't do it can it? you can just load a bunch of stuff into the registers normally and do an operation on all of them at once
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May 13, 2017 03:59
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avx makes your chip really hot so i dont think the bus is the issue
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May 13, 2017 04:15
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The Management posted:it also has strict memory ordering that creates horrible unnecessary dependencies don't tso-shame
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May 13, 2017 06:22
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some intel chip dude posted:One that sticks out in my mind is when the Itanium effort was just getting going. We Oregonians were being systematically and purposely excluded from that effort. HP was worried that HP had brought some kind of intellectual property to the table for Itanium, and they did not want to see that IP appear in a competing line of x86 processors. So at the time they were being very careful to separate these two apart. We therefore knew very little about what Itanium was, we just heard rumors that it's kind of like a VLIW, which is what we did at Multiflow. Papworth and I would look at each other and think, as far as we know there are only two people in this company who know anything about VLIWs and that's the two of us. the whole interview is good if you're into that sorta thing http://newsletter.sigmicro.org/sigmicro-oral-history-transcripts/Bob-Colwell-Transcript.pdf
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May 13, 2017 07:36
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travelling wave posted:the whole interview is good if you're into that sorta thing executives.txt
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May 13, 2017 12:22
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I CANNOT EJACULATE WITHOUT SEEING NATIVE AMERICANS BRUTALISED!
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Also why is HP actually going to ship anything with new itanium cores in 2017, are there seriously IT departments that transitioned mission-critical poo poo onto Itanium a decade ago and want to keep their dead gay system running on second-rate hardware until the end of time just so they never have to transition it back?
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May 13, 2017 12:39
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probably
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May 13, 2017 13:57
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blowfish posted:Also why is HP actually going to ship anything with new itanium cores in 2017, are there seriously IT departments that transitioned mission-critical poo poo onto Itanium a decade ago and want to keep their dead gay system running on second-rate hardware until the end of time just so they never have to transition it back? yes. itanium is the new mainframe. companies are stuck on it running their hpux and vms systems on slow, expensive hardware because migrating is basically impossible.
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May 13, 2017 14:02
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blowfish posted:Also why is HP actually going to ship anything with new itanium cores in 2017, are there seriously IT departments that transitioned mission-critical poo poo onto Itanium a decade ago and want to keep their dead gay system running on second-rate hardware until the end of time just so they never have to transition it back? a ton of 1990s HP-UX users migrated from HPPA to Itanium because HP forced them to do so. HP end-of-lifed all HPPA products, so it was itanium or nothing migrating off legacy unix can be really hard. especially if you don't really care about the money you pay your vendor. it's much easier to write a fat check than get neck-deep in code archeology
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May 13, 2017 14:30
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The Management posted:yes. itanium is the new mainframe. companies are stuck on it running their hpux and vms systems on slow, expensive hardware because migrating is basically impossible. hpe sold openvms to a new company, "vms software inc" their main goal is to port openvms to x86 by 2018
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May 13, 2017 14:32
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you can't spell shitheap without hp!
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May 13, 2017 17:02
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Notorious b.s.d. posted:hpe sold openvms to a new company, "vms software inc" lmbo do not tell the power sector the last thing they need is a way to keep limping along their early 90's HMI platforms
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May 13, 2017 17:09
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travelling wave posted:the whole interview is good if you're into that sorta thing this is a really good read, thank you
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May 13, 2017 19:25
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BangersInMyKnickers posted:lmbo do not tell the power sector the last thing they need is a way to keep limping along their early 90's HMI platforms early 90s? all the banking and healthcare still on z/arch would like a word i mean, it's not like it doesn't _work_, it's just old as balls
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May 13, 2017 23:50
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travelling wave posted:the whole interview is good if you're into that sorta thing thx for this, found this gem too quote:0:27:22 BC: That never happened. Instead, for example five Intel fellows including me went to visit Craig Barrett in June of 98 with the same Itanium story, that Itanium was not going to be able to deliver what was being promised. The positioning of Itanium relative to the x86 line is wrong, because x86 is going to better than you think and Itanium is going to be worse and they're going to meet in the middle. We're being forced to put a gap in the product lines between Itanium and x86 to try to boost the prospects for Itanium. There's a gap there now that AMD is going to drive a truck through, they're going to, what do you think they're going to hit, they're going to go right after that hole" which in fact they did. It didn't take any deep insight to see all of these things, but Craig essentially got really mad at us, kicked us out of his office and said (and this is a direct quote) "I don't pay you to bring me bad news, I pay you to go make my plans work out".
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May 14, 2017 14:56
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blowfish posted:executives.txt quote:
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May 14, 2017 17:19
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Salt Fish posted:Wait, what is the storage technology called? Pentanium? Or something? Optanium? http://www.intel.com.au/content/www/au/en/architecture-and-technology/intel-optane-technology.html
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May 15, 2017 13:58
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rjmccall posted:arm64 is a really nice isa. in contrast, risc-v is garbage trash for idiots if you don't mind could you elaborate on why riscv is trash?
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May 15, 2017 14:46
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ate all the Oreos posted:i would really like to see a new big deal processor architecture that's not ARM or x86 some time just because i think it would be real interesting and the way computers do things has changed a bunch since the loving 1980's but that's never gonna happen lol my man have you heard of this revolutionary new "mill architecture"
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May 15, 2017 17:07
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joking aside, SPARC64 XII is cool as all hell. don't even step unless your CPU has dedicated SQL cores
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May 15, 2017 17:09
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Mr.Radar posted:if you don't mind could you elaborate on why riscv is trash? the core isa is super-riscy in that "yay we can run a lot of instructions now which is important because it'll take us twice as many instructions to do anything" sort of way. they made sure they covered all the basic c operations but anything even closely related like add-and-test-overflow or add-witih-carry is impossible to do efficiently with the base instructions. but mostly it's like, just read the instruction specifications and you'll see all sorts of bizarre and wasteful crap like the branch-immediate instruction (jal) has a 20-bit immediate operand, but it's stored in a crazy order where 0bTSRQPONMLKJIHGFEDCBA is actually reordered as 0bTJIHGFEDCBAKSRQPONML for as far as i can tell no reason at all. instructions are 32-bit so the pc is generally required to be 4-byte-aligned but the immediate offset is only implicitly multiplied by 2 so the instruction only has ±1MB range instead of ±2MB. instead of burning 1 bit on branch vs. branch-and-link it burns 5 bits so that you can use an arbitrary gpr as the link register (but you won't get return-address prediction unless you use x1), which i can kindof imagine ways to use but not for anything important enough to justify dropping 4 bits from the range of this instruction. and really it should be 5 because both of these are super-common instructions and it's worth burning a second opcode on them ok, next. the branch-register instruction (jalr) takes a 12-bit immediate offset. that offset is not scaled at all. the lowest bit of the target address is defined to be ignored, but not the lowest two bits so this can still fail dynamically from mis-alignment. as far as i can tell this immediate exists solely because they wanted to use a two-operand instruction format; i am really blanking on what it would be used for. the spec suggests it could be used to implement fast library calls by doing absolute branches to ±2KB, which is like, yes please let me just give memcpy a small integer absolute address, i am doing research into how easy i can make it to write security exploits
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May 15, 2017 18:20
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atomicthumbs posted:joking aside, SPARC64 XII is cool as all hell. don't even step unless your CPU has dedicated SQL cores as/400: you rang?
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May 15, 2017 18:34
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atomicthumbs posted:joking aside, SPARC64 XII is cool as all hell. don't even step unless your CPU has dedicated SQL cores lol we had some solaris servers, but they were the ones with more threads for webservers iirc they were being used as database servers 
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May 15, 2017 18:38
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rjmccall posted:the core isa is super-riscy in that "yay we can run a lot of instructions now which is important because it'll take us twice as many instructions to do anything" sort of way. they made sure they covered all the basic c operations but anything even closely related like add-and-test-overflow or add-witih-carry is impossible to do efficiently with the base instructions. but mostly it's like, just read the instruction specifications and you'll see all sorts of bizarre and wasteful crap sounds like it was written by a bunch of academics with weird little bullshit pet reasons for all the quirks oh wait it was wasn't it
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May 15, 2017 21:42
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gonna change my name to RISCy business
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May 15, 2017 21:48
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lowtax appreciates your donation
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May 15, 2017 21:52
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Endless Mike posted:lowtax appreciates your donation i already bought tekken 7 so i have nothing better to spend my money on
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May 15, 2017 21:53
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carry on then posted:as/400: you rang?  call me when as/400 gets 8 threads per core with 12 cores at 4.35 ghz  edit: die size of 795 mm2
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May 15, 2017 22:48
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what the heck is software on chip
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May 15, 2017 22:49
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Bloody posted:what the heck is software on chip various acceleration implemented as RISC instructions instead of coprocessing units   
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May 15, 2017 23:10
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is an oracle number a really enterprisey number?
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May 16, 2017 00:40
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atomicthumbs posted:
i was a gonna say they were doing it in the 80s but apparently power9 does have 12x8 @ 4ghz so possibly 
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May 16, 2017 00:55
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mishaq posted:is an oracle number a really enterprisey number? if you have to ask you can't afford it
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May 16, 2017 04:54
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Salt Fish posted:Wait, what is the storage technology called? Pentanium? Or something? Optanium? tane
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May 16, 2017 05:36
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quantx
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May 16, 2017 10:23
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itanium is like this kinda cool totally worthless 
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May 16, 2017 10:34
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counterpoitnt : itanium is alive
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May 16, 2017 21:07
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