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echinopsis posted:can someone give me an explain like i'm 5 yes
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May 11, 2017 22:40
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| # ¿ May 16, 2024 15:16 |
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itanium has been dead for years. its VLIW instruction set was garbage and it tried to pawn off a whole bunch of difficult problems on the compiler. well, a compiler that solves those problems well never appeared because it's much harder to solve the problems at compile time than at run time. so while theoretically it was faster in practice it was terrible running real code. it was routinely spanked by x86 processors while using more power. basically it was a total disaster.
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May 11, 2017 22:55
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fritz posted:one of the things im doing at work is writing assembly code for a vliw chip, the isa is much more explicit than what ive seen of itaniums, but it's still some serious black magic to get it working well hexagon?
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May 11, 2017 23:10
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ate all the Oreos posted:i would really like to see a new big deal processor architecture that's not ARM or x86 some time just because i think it would be real interesting and the way computers do things has changed a bunch since the loving 1980's but that's never gonna happen lol arm64 is an entirely new architecture that shares very little with the 32-bit arm ISA. it is designed for modern, high end processors.
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May 12, 2017 03:33
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ate all the Oreos posted:eh i guess, i was hoping for something more x86-y with a million loving instructions and extensions and stuff but that's garbage and actively defeats modern microarchitectures.
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May 12, 2017 03:35
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rjmccall posted:x86 is a terrible isa but it's not because it's got a million instructions, it's because it's a variable-length unaligned format with a ton of prefixes and suffixes and special case operand encodings many of which vary depending on the current processor mode, so you can't even figure out where the next instruction starts without fully decoding the current one which is extremely complex to do it also has strict memory ordering that creates horrible unnecessary dependencies, exacerbated by instructions that directly reference memory operands (I know the uarch doesn't but it still has to maintain their transactional order for writeback). the register use in the ABI is awful. 16 registers and half of them are almost never touched in generated code.
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May 12, 2017 22:06
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fritz posted:no, and bossman gets testy when i say too much, once things get public rest assured i'll post in the terrible prog. thread about it no, post to a good thread
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May 12, 2017 22:10
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qkkl posted:I thought Intel's plan was to have Itanium be 128-bit so more data could be loaded into the registers from RAM, and you could do things like double the number of 64-bit multiplies in one clock cycle compared to 64-bit processors. most modern processors have 128-bit or larger vector registers that can do this, including x86_64
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May 13, 2017 03:00
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| # ¿ May 16, 2024 15:16 |
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blowfish posted:Also why is HP actually going to ship anything with new itanium cores in 2017, are there seriously IT departments that transitioned mission-critical poo poo onto Itanium a decade ago and want to keep their dead gay system running on second-rate hardware until the end of time just so they never have to transition it back? yes. itanium is the new mainframe. companies are stuck on it running their hpux and vms systems on slow, expensive hardware because migrating is basically impossible.
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May 13, 2017 14:02
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