Non-x86 Platforms Thread: for all your ARM, RISC-V, SPARC, and PDP-11 needs

The Something Awful Forums > Discussion > Serious Hardware/Software Crap > Non-x86 Platforms Thread: for all your ARM, RISC-V, SPARC, and PDP-11 needs

minidracula: Dec 22, 2007; boo woo boo

Why did I only find this thread like less than ~30 minutes ago? Y'all are my people. I'm home.

# ¿ Oct 30, 2023 09:46

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# ¿ May 14, 2024 15:43

minidracula: Dec 22, 2007; boo woo boo

Haven't had as much time as I've wanted to post ITT re: some weird stuff and reply to others, but, just out of curiosity: anyone else here used or messed around with Parallax Propeller 1 or Propeller 2 parts?

# ¿ Jan 31, 2024 08:25

minidracula: Dec 22, 2007; boo woo boo

eschaton posted:

I found some more Inmos T805 Transputer CPUs in a box in my office

along with an Inmos VMEbus board fully decked out with CPUs-less TRAMs

also a couple decked out with TRAMs that do have CPUs installed

I think it may be a signal from past me to write some Occam-2 or something

Gimme!

(You should write some occam-2/occam-pi if you haven't already, Transputers or not, just for the hell of it.)

# ¿ Mar 6, 2024 22:34

minidracula: Dec 22, 2007; boo woo boo

eschaton posted:

I just set up an m88k-interest mailing list for people still interested in the Motorola 88000 series

Please sir, can you spare a LUNA?

# ¿ Mar 8, 2024 00:36

minidracula: Dec 22, 2007; boo woo boo

BobHoward posted:

I wonder how much 88K Macintosh hardware is out there.

(for those who don't know, when Apple was investigating options for transitioning away from 68K, 88K was one of them, and it got as far as them manufacturing a bunch of prototype 88K Macs for software development work.)

Actually I wonder how much 88K hardware is out there at all. Not a wildly successful ISA!

From what I understand when I last looked into it, MVME was probably the most manufactured and deployed m88k form factor? Data General also originally built AViiON systems on m88k, before switching to x86 (Pentium-era, initially, I think). There were some other small scale users, OMRON's LUNA being another, mostly in Japan, and some use in telcos, etc. (Nortel had some use of m88k in some part/version/edition of DMS at one point). Beyond that I'm not sure. I know some CMU folks used m88k for some Mach projects. The sense I got was once AIM "took off" and settled on PowerPC, m88k was well and truly dead inside Motorola, and it had already had a late start compared to SPARC and MIPS in the RISC space of the era, etc., etc.

I didn't know about the prototype Mac m88k HW at all, or that they even did that!

# ¿ Mar 8, 2024 01:52

minidracula: Dec 22, 2007; boo woo boo

Speaking of weird architectures, and since I'm not done with other would-be effortposts stuck in draft states, anyone else here other than me have any GreenArrays boards or parts?

# ¿ Mar 8, 2024 02:08

minidracula: Dec 22, 2007; boo woo boo

Subjunctive posted:

it�s OK

does anyone know what kind of FPGA you need to run the CHERI implementation?

VCU118 IIRC is what they used as the dev board for CHERI ISAv9 CHERI-RISC-V implementations (CHERI-Piccolo, CHERI-Flute, and CHERI-Toooba), see: https://www.xilinx.com/products/boards-and-kits/vcu118.html

I think you can get away with less esp. with the smaller RISC-V BSV implementations (Piccolo, Flute), I'm trying to. We should maybe chat!(?)

EDIT #1: the specific AMD/XIlinx UltraScale+ part on the board is the XCVU9P-L2FLGA2104E.

EDIT #2: I'm assuming you didn't mean the CHERIoT effort (e.g., https://cheriot.org/) since you said CHERI, but just in case you did, or didn't necessarily mean to exclude it, they're building on (at least) a Diligent Arty A7-100T board (see https://cheriot.org/fpga/try/2023/11/16/cheriot-on-the-arty-a7.html && https://github.com/microsoft/cheriot-safe), specific part: XC7A100TCSG324-1.

minidracula fucked around with this message at 06:32 on May 8, 2024

# ¿ May 8, 2024 06:08

minidracula: Dec 22, 2007; boo woo boo

karoshi posted:

There are also cheap smart NICs based on FPGAs being decommissioned by the cloud providers which you can find in ebay. Stuff like
https://www.ebay.com/itm/185659756161, https://www.ebay.com/itm/144113217470 and https://www.ebay.com/itm/275258652279. Some of those FPGAs are non-standard and you'll need to use the non-free vendor tools. It's quite a rabbit hole, but some very enthusiastic enthusiast have gotten some of those to work.

The altera/intel Arria parts have hard-FPUs (float32 MAC, IIRC) which can save you some resources, if you feel like integrating them into the upstream IP. This would be specially useful for implementing GPUs.

And to think I was involved in one of the v1/v0 iterations of a thing that later led to Catapult...

# ¿ May 8, 2024 07:53

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# ¿ May 14, 2024 15:43

minidracula: Dec 22, 2007; boo woo boo

There's this WRT PPA for a specific build of cheriot-ibex (so CHERIoT, and not any of the CHERI-RISC-V designs built on top of Piccolo, Flute, or Tooba), but I wouldn't necessarily read much into this for CHERI-RISC-V, due to a bunch of variables:

quote:

Timing, area and power

A PPA study conducted at Microsoft shows that cheriot-ibex is similar to the original ibex design in terms of area and power, however with moderate increase in area.

cheriot-ibex (configured as 3-stage pipeline) has been synthesized successfully using Synopsys DC-topo at 250MHz using TSMC 28nm (28LP) libraries (ss 1.03v) and 550MHz using TSMC 5nm (N5) libraries (ss 0.6v). Timing is mostly limited by TCM read access time (which approaches 1.6ns in the N5 case).

The design area is ~60k gate equivalents (~25% more the original ibex design). Both dynamic and leakage power are shown as similar to the original ibex design.

I think I have some numbers for "stock" (non-CHERI) Piccolo, Flute, and Tooba cores laying around from some of my experiments, but not ready to hand. I'll see if I can find them, or maybe just do some fresh synthesis runs. Again, wouldn't necessarily tell you much re: CHERI, but would feasibly give you a reasonable lower bound for each, since CHERI's just gonna add more.

I'm willing to bet the VCU118 is an over-provisioned board & part in general too, sure, but I guess I don't know that. I mean, it's what I'd do. Especially for multiple different core designs. And they may have been using the same board for ISAv8 and prior ISA versions and/or ARM and/or previous MIPS work. That said, I did do some very brief quick & dirty searching to see if I could turn up utilization numbers, and didn't find any re: CHERI-Piccolo, CHERI-Flute, or CHERI-Tooba, on that board/part or another, but it was a brief and very surface level search, so I'll see if I can dig up better numbers later.

EDIT: OK, so I found some numbers while eating a late lunch microwaved freezer burrito:

quote:

Baseline Performance

PPA
Run the ./get_ppa.py script to get numbers measured by Vivado, for example:

code:

$ ./get_ppa.py vivado/soc_bluespec_p1/soc_bluespec_p1.runs/impl_1/
{"power_W": 0.25, "CLB_LUTs": 90341, "CLB_regs": 118324, "cpu_Mhz": 50.0}

Baseline values as of GFE 4.x release:

pre:

processor      power_W    CLB_LUTs    CLB_regs    cpu_Mhz
_________________________________________________________
Bluespec P1    0.25       90341       118324      50.0
Bluespec P2    0.302      121254      128260      100.0
Bluespec P3    0.365      343698      250477      25.0
Chisel P1      0.267      84043       113347      50.0
Chisel P2      0.457      131524      188846      100.0
Chisel P3      0.37       188629      156332      25.0

Source: https://github.com/CTSRD-CHERI/BESSPIN-GFE?tab=readme-ov-file#baseline-performance

You'll be helped out by this PDF from 2020 <https://github.com/CTSRD-CHERI/BESSPIN-GFE/blob/cambridge/GFE_Rel5.2_System_Description.pdf> which describes the hardware in some useful ways ("GFE", here, if you're wondering, stands for "Government Furnished Equipment"). For our uses re: the table above, pp. 4-5 serve as a decoder ring to make sure we know what "P1", "P2", "P3" -- whether prefixed by either Bluespec or Chisel -- mean in context: Bluespec P1 is CHERI-Piccolo, Bluespec P2 is CHERI-Flute, Bluespec P3 is CHERI-Tooba.

The same document shows what else is being instantiated on the UltraScale+ part, including supporting Xilinx IP (unsurprising).

minidracula fucked around with this message at 00:13 on May 9, 2024

# ¿ May 8, 2024 23:10

The Something Awful Forums > Discussion > Serious Hardware/Software Crap > Non-x86 Platforms Thread: for all your ARM, RISC-V, SPARC, and PDP-11 needs