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JawnV6 posted:I designed something with a MSP430, it had a capacitive sensor. I hate MSP430s. Used them in space applications (at the time, it was the 'lol FRAM is invincible logic') and ran into the same issues as above, but due to I2C. No built in CAN controller also sucked. FRAM is destructive reads, so IIRC, at least the FR5969 had a stupidly large amount of die area spent on capacitance to help not corrupt itself upon power loss. Also -- thanks for this thread appearing! I had typed up a vague OP with a list of random archs to toss out for discussion, but it's now lost to the ages. Anyone use any of the weird Japanese market uArchs? NEC V850s were popular in automotive for a short bit of time -- I'm still fascinated by how many of those uArchs are still running around even with Cortex-M eating everything. That market tends to be insular / leverage local suppliers, so some of those are gonna be around for awhile.
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Aug 7, 2021 20:12
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Selklubber posted:What kinda cool space stuff did you work on? Is CAN-bus used for space applications too? Mostly CubeSats / small spacecraft, and then one deep-space mission before everything ran out of money. People are making rad-tolerant CAN transceivers now, so it’s gaining a bit of traction with the newer players. Other common space architectures are SPARC, and a few folks are getting ARM and RISC-V up-to-snuff to get flying. POWER of course is represented — RAD750 runs both Curiosity and Perseverance.
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Aug 9, 2021 06:44
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corgski posted:Anyone here know much about Intel i960? I've used a bunch of equipment built around that chip, most of which was an upgrade from the company's previous hardware platform of multiple z80-based uCs (Hitachi HD64180) and a TI TMS320C20. IIRC it was a victim of politics / lawsuits, but it was popular in RAID controllers, military applications and its design-intent was to support high-reliability applications by designing silicon around the expected usage of very high-level languages like Ada where memory safety, garbage collection and so on were all first class citizens.
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Aug 9, 2021 07:35
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Someone on Twitter found a "RISC-V High Performance Engineer" job posting from Apple -- what are they up too, I wonder...
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Sep 2, 2021 22:27
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priznat posted:Wow. I had seen some article header about RISC-V multicore linux capable cpus and wonder if that’s what they’re getting into first perhaps. Something in the data center (no idea what) or perhaps a new wifi base station powered by one? They clearly have good ‘little’ ARM cores, but I wonder if they’re looking for something NVIDIA Falcon like, where it supports NoCs / things like that. Seems perfect to brew your own RV32/RV64 and pay $0 licensing / royalties.
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Sep 2, 2021 23:51
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priznat posted:Yeah very interesting especially if they can stamp them into other silicon for some built in telemetry or control plane. Security processor perhaps hence the performance? Sky’s the limit really. Oh — duh, maybe in their baseband processors for the inevitable Apple modems!
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Sep 3, 2021 00:10
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eschaton posted:Apple was one of the original investors in ARM and it wouldn’t surprise me if they got a perpetual platform license out of it. Yeah, I thought I remembered reading that they have one of the few perpetual / arch licenses. Otherwise I feel they would have started heading away from ARM already / not invested as much into developing their own ARM cores.
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Sep 4, 2021 20:19
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priznat posted:It’s interesting as a lot of SoCs are moving away from Arm to Risc-V, I imagine the sale falling through may slow it down a little bit as Arm may be more willing to get competitive with licensing fees? The Falcon (embedded GPU control processor / security stuff) is RISC-V I’m pretty sure. For Tegra and friends though, they have the perpetual ARM architecture license still, right?
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Feb 12, 2022 19:44
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NewFatMike posted:Aren’t traffic lights the big standout MIPS thing still remaining? I’m sure there’s plenty, but that stuck out to me if my recollection is correct. Cavium Octeon SoCs are MIPS IIRC, and is fairly prevalent in networking. I think some MediaTek WLAN SoCs might be MIPS as well. I figured one of the driving factors in RISC-V adoption would be the royalty-free ecosystem — appealing to folks paying for Cortex-A/M licenses.
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Feb 14, 2022 11:06
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feedmegin posted:This is the sort of thing I'm thinking of...we used to support an Octeon-based network appliance 3 jobs ago. Then we didn't any more because they got retired (the new version was ARM), and this was ~5 years ago. Hmm — not like the EdgeRouter 4 is the absolute cutting edge of networking technology, but it’s still sold today / is in Ubiquiti’s nominal line-up and I’m like 98% sure when I cat /cpu/procinfo it, it’s a MIPS-based Octeon. One of the strong points of MIPS (IIRC) was the relative ease in which co-processors plugged right into the architecture; PS1/PS2 used this to great-effect. Or, Cavium just happened to have an architecture team / engineers who were familiar w/ MIPS, the licensing price was right, and so it was done.
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Feb 14, 2022 16:31
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ploots posted:Every fpga dev I know has been talking about riscv for years. I think it’ll take hold in soft cores and fpga focused SoCs, even if it fails to take off in embedded more broadly. HDD controllers (WD) was one place they were going after it, and I'm sure various SoC designs will consider it vs. dropping an -A9 or -M4/M7 anywhere a core is needed. Didn't NVIDIA at one point have some stupid amount of -A9s in their design? Though, I'm partially convinced those guys just burned die area in the interest of speed to market.
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Oct 15, 2023 18:54
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priznat posted:High speed PHYs have arm/RISCV cores on each lane for equalization and station keeping so they can really explode the number of cores in an SoC! 100G+ / PCIe 5.0 type stuff? Do they run FW that's loaded at runtime / are the algorithms now more suited for a CPU implementation / branchiness vs. using a FSM like the lord intended?
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Oct 15, 2023 19:35
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eschaton posted:what we need is a way to trick software people into writing something that looks like “normal” software but which is actually an FSM that can be formally verified I dream of this... replace software with a FSM that I can formally verify and is deterministic as long as the laws of physics don't change.
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Oct 17, 2023 05:39
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JawnV6 posted:I always think about the kind of folks who can tie specific CPU architecture features to things like how many layers the PCB needs. Sure you can distribute that decision into a team or 5, but.. I've met individual people who could do that kind of thing no sweat. Specialization is very important in certain areas but "systems thinking" is a common trait in the highest-performing people I've worked with. If you can connect a narrative thread behind your CPU uarch / silicon designs to the package impacts to the implementation requirements on the PCB in your brain, that's a superpower -- don't need a team of systems engineers managing requirements. "This SKU must be low cost -> package constraints -> needs to be implementable on 4L PCBs at the cheapest fab imaginable -> constrain to 0.8 mm pitch BGA -> pick FCBGA -> can't do insane amounts of power or high-speed I/O given those constraints -> etc" Chiplets might be one of the best things that's ever happened for being able to play LEGO on the chip package itself -- and everyone is getting better at the innovation / development required to make that a good idea (inter-chiplet comms / etc).
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Dec 24, 2023 21:03
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I thought I read at some point it was… questionably licensed Xtensa but on paper, RISC-V implementations should be “cheaper” with no ARM license costs. Now of course, ecosystem support etc etc on top of that… but I also have no idea how much a Cortex-M0/4 license actually costs.
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Dec 25, 2023 18:59
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