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There's still a bunch of botique ISAs running around in the microcontroller world, although cortex-m has been eating them one by one. The ones I've worked with directly: NXP Coldfire: not-quite-a-68k 32-bit micro that's similar to but not binary compatible with 68000. Mnemonics mostly the same but the opcodes changed, with a few additions and subtractions. Beefy enough to run uclinux in '99 then full-blown linux with mmu on coldfire v4 in 2000. Not a whole lot to say about the ISA since it was a slightly optimized variant on the extremely popular 68k. Dropped binary coded decimal support and tweaked a few other things. It's being phased out for Cortex-A/Cortex-M parts but they still sell them up to 266mhz. Microchip PIC: grandad's microprocessor Love them or hate them, they're absolutely everywhere. The earlier 8-bit parts were interesting to program for in anything but assembler given the c-hostile ISA. Single accumulator, N-banks of 256 8-bit registers that serve as ram. No access to the hardware stack so it's only usable for ISRs and of course your "software stack" is using the same registers you're trying to push. All registers have to be accessed directly, with a pair of hardware registers to do indirect addressing. Eventually the indirect addressing was extended to add post-increment. Before that you had to manually increment FSR to get the next byte of an array. I hated working with them. TI MSP430: seemingly operates on unicorn farts, not electricity Can run for literal years on a single coin-cell due to the hyper-optimized wake/sleep cycles. 16-bit von neumann with an enormous variety of peripherals, pinouts, operating frequencies and sram capacity. 16 registers, with PC/SP/SR and hardcoded-zero being the first 4 and addressed the same as the 12 following general purpose regs. Two dozen or so opcodes so not a lot of core complexity to deal with, until you've got more than 64k of addressable storage. Then things start to get weird, since it doesn't have virtual memory. If you needed a small amount of code over what was partitioned on your particular chip you could just copy it to a fixed (low) SRAM location and jump to it. If you needed more than that, you got to enjoy the wild word of overlays and trampolines. To call a function in high-flash you had to copy it to low SRAM then jump to it. The next function? Yup, copy that bank in and jump to the same address, now with new code. This was always a source of excitement when debugging. This is different than segmented processors like the 8086 in that it required a memory copy rather than just changing a bank register. AVR (Alf and Vegard's RISC processor): Basis of the arduino phenomenon and 3d printers everywhere. 8-bit harvard architecture with 32 registers. Probably the one i've worked the most on, entirely due to a quirk of timing that the UART perhiperal supported 9-bit serial when the other options needed to bit-bang without hardware support. Instruction set is fairly sane, mostly-general-purpose registers with a few special meanings. There's a few quirks to be aware of, such as flags only being affected by specific instructions and not always the ones you'd expect. Different opcodes for the different addressing domains, IO/register file/SRAM/EEPROM/flash. Flash is word-addressed so you can directly load from 128k. Since so much addressing is 16bit there's MOV.W instructions added later that set register pairs at once. A slight revamp/cleanup of the addressing modes was done for the "xmega" line but they're fundamentally the same. Supports every perhiperal under the sun, including USB (device). Also owned by microchip now. I'm probably forgetting some but this post is already way too long.
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Jul 25, 2021 09:43
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| # ¿ May 16, 2024 02:44 |
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