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The Something Awful Forums > Discussion > Serious Hardware/Software Crap > YOSPOS > show/tell me about DEC hardware (and x86 memory management)
 
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EIDE Van Hagar
Dec 8, 2000

Beep Boop

Good Sphere posted:

my dad worked there for 20+ years, before moving onto Intel when they were bought up :)

i had a poster on my bedroom wall of the alpha processor

his mother asked him to look for a job. he opened up a phone book and saw digital equipment corporation and said "oh computers. i've heard of these". he first worked with hardware assembly, then was an instructor for various things, including using oscilloscopes, until he went onto technical writing. he made a silly (but very inspiring) video on a weekend there in his early days. there was a production rental department where he got cameras, and made a video about him stuck in a microprocessor, a journey through the manufacturing plant, and something with someone dressed in a gorilla costume. gotta post it someday

this should reallt really all be on youtube

* # ¿ Jan 18, 2022 15:57
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# ¿ May 22, 2024 05:35
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EIDE Van Hagar
Dec 8, 2000

Beep Boop

Farmer Crack-rear end posted:

i remember my dad being grumpy about "turbo" being used as a word for "fast"

"oh is there a turbine involved? no?? so why did you use the word turbo?!"

i got really really mad once when the nyt crossword tried to use “supercharged, as am engine” as a clue for “revved”. i remember a lot of website comments with other angry car people saying “you can rev any car but ‘supercharged’ has a specific technical meaning that implies use of a supercharger, which is orthogonal to throttle input”

* # ¿ Jan 18, 2022 16:01
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EIDE Van Hagar
Dec 8, 2000

Beep Boop
having 21 address bits is physically impossible

* # ¿ Jan 31, 2022 18:30
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EIDE Van Hagar
Dec 8, 2000

Beep Boop

Kazinsal posted:

okay, time to talk about x86 memory management. this post is going to get a bit out of hand so I'm breaking it into sections.


way back before the 8086 the 8080 family had a 16-bit address space but no internal mechanism to manage it, so if you wanted more than 64KiB of RAM/ROM/MMIO you needed an external chip that you could frob to switch what a certain range of the address bus actually pointed at. this sucked but a lot of 8-bit CPU families did this and the chips are fairly simple. you hook them up to say a 16 KiB window and expose a couple I/O ports to the CPU so software can switch that 16 KiB bank to a different slice of whatever RAM chip is hooked up to it through the bank selector chip.

so when Intel designed the 8086 they realized how badly this sucked and even though they were still making a 16-bit CPU they stuck 4 more address lines onto it so they could basically do a sort of pseudo bank switching system in the standard address decoding logic. the 8086 has four 16-bit segment registers that are used in the address decoding logic to create a 20-bit address from a 16-bit segment and a 16-bit offset (usually formatted in documentation as eg. 1234:CDEF, where the word before the colon is the segment and the word after it is the offset. the logic is pretty simple: the segment word is shifted four bits to the left and the offset is added to it. in the above example we'd get this:

code:
segment << 4 | 12340
    + offset |  CDEF
------------ | -----
   = address | 1F12F
this is super advantageous over the bank switching chip thing for two reasons: one, you get full access to the whole 20-bit address space of the system at all times, and two, your code can always assume it starts at 0000 and goes to however much memory it needs in a 16-bit space since the OS can just give you a block of memory and say "your segment is 0x1234". all your indexes and offsets are from 0, no matter where in the 20-bit address space you actually are! and you get separate selectors for code (CS), data (DS and ES), and stack (SS), and segment override prefixes so you can access up to four 64K segments at any time without reloading the segment registers


i did some of the validation for the ILB “Intel Legacy Block” on an Atom SoC, that is, the integration of the block into the SoC. the ILB handles a bunch of legacy boot flows and and this post is giving me flashbacks to reading ISA and PCI specs

* # ¿ Feb 1, 2022 22:04
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EIDE Van Hagar
Dec 8, 2000

Beep Boop
low low value male

* # ¿ Feb 2, 2022 10:32
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# ¿ May 22, 2024 05:35
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EIDE Van Hagar
Dec 8, 2000

Beep Boop

Kazinsal posted:

scsi2sd will be here next week, AUI transceiver the week after, and the VAX and console cable should be here the week after that

dear ebay seller: sned the yosvax

i gotta say i respect this commitment to silly irrelevant old computer platforms because the same brain disease is why i have my pismo powerbook running mac os 9

* # ¿ Feb 15, 2022 19:39
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The Something Awful Forums > Discussion > Serious Hardware/Software Crap > YOSPOS > show/tell me about DEC hardware (and x86 memory management)