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movax posted:fpga tooling on linux is only good for running headless builds imo; if you need to use the gui at all, stick with windows. linux is a second-class citizen (as it should be) headless builds should be the default
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Mar 13, 2015 22:06
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Poopernickel posted:it puts the P in PVT lol
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Mar 13, 2015 22:06
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Bloody posted:hope those opencores vhdl blocks work lol the other way
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Mar 13, 2015 22:06
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i rewrote them in verilog and now i can simulate against them and they seem to work mostly 
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Mar 13, 2015 22:18
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what's ur simulator? icarus?
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Mar 13, 2015 22:21
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a crippled version of modelsim
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Mar 13, 2015 22:26
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where can i get a 24V 250mA 6 pin mini DIN power supply for this? http://www.ebay.com/itm/KINETRONICS-SV-4400U-STATIC-FREE-STATICVAC-PHOTO-FILM-CLEANER-IONIZING-DUST-/361234782853 i foudn this but i dont want to pay $35 for a power supply http://poweradapter.co/kinetronics-sc102ta2400f01-ac-adapter-24vdc-075a-used-6pin-9mm-p-1687.html thank you!! 
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Mar 16, 2015 20:38
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if your time is worth minimum wage you can get a 12-18 1a adapter and a shenzhen stepup board and a 6 pin mini din. otherwise just buy the psu
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Mar 16, 2015 20:48
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yea 24v is pretty uncommon in surplus, so either get lucky on ebay or at a flea market, or diy, or pay for the right one
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Mar 16, 2015 20:51
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two car batteries in series
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Mar 16, 2015 21:06
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Bloody posted:two car batteries in series or do like a flying capacitor boost converter except with a deep cycle marine battery instead of the capacitor
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Mar 16, 2015 21:11
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Jonny 290 posted:if your time is worth minimum wage you can get a 12-18 1a adapter and a shenzhen stepup board and a 6 pin mini din. otherwise just buy the psu yeah good point i did find this http://www.amazon.com/gp/product/B000KKO3PI/ cause i dont like DIYing power stuff
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Mar 16, 2015 23:40
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Chill Callahan posted:where can i get a 24V 250mA 6 pin mini DIN power supply for this? $35 is cheap
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Mar 16, 2015 23:55
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I am pleased to report that blocks which worked in simulation do not work in the real world
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Mar 17, 2015 05:51
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Bloody posted:I am pleased to report that blocks which worked in simulation do not work in the real world this is always fun. the first thing i ever wrote went straight into production at my company because it replaced registers with block ram which resulted in great logic usage savings. of course it worked beautifully in simulation and even in my initial in hardware test. but let the FPGA get over 80 °C or configure the module in a certain way and yay total failure. turns out that checking for an event, generating a new address for a block ram and reading the associated value in a single combinatoric path at 108 MHz isn't exactly the smartest idea. that took a few sleepless nights to fix if you have never written code for synthesis before. in hindsight, gently caress my colleagues for letting an intern with three weeks of experience do such a thing in the first place.
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Mar 17, 2015 19:31
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from reading this thread, i am no longer interested in FPGA design
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Mar 17, 2015 19:47
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karasu posted:of course it worked beautifully in simulation and even in my initial in hardware test. but let the FPGA get over 80 °C or configure the module in a certain way and yay total failure. spec commercial, not automotive, WONTFIX, WORKSINMYENVIRONMENT
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Mar 17, 2015 19:50
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atomicthumbs posted:from reading this thread, i am no longer interested in FPGA design i am but it seems like a tough gig to break into also microcontrollers and socs being what they are these days it seems there aren't that many places where asics or fpgas are cost-effective
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Mar 17, 2015 20:14
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video processing one mipi port? two cameras? wow, no way we could buy a mux, better slap a FPGA on there
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Mar 17, 2015 21:03
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read a switch AND flash an LED? looks like we're going to need at least a dual-core cpu for this thing
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Mar 17, 2015 21:25
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why don't they just make 1 chip that does everything really well, like super low power, lots of teraflops or whatever and small and doesn't need any active cooling
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Mar 17, 2015 21:27
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the closest Real Thing to that is a bunch of pin-compatible parts from different micro lines, like a M0 and a M4 that can be reworked after layout
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Mar 17, 2015 21:51
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cell phone socs have a bunch of stuff that would be an ASIC in the past, image processors, video encoders/decoders, display blitters and so on, if you want to do that.
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Mar 17, 2015 22:13
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i want the same chip in my smart watch that's in my supercomputer cluster
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Mar 17, 2015 22:23
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Mr Dog posted:i am network processing and packet inspection no way you can do meaningful operations on a 40gb or 100gb line going full speed in anything but an fpga (or an asic)
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Mar 17, 2015 22:26
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Mr Dog posted:i am bitcoin mining :iamafag:
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Mar 17, 2015 22:52
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Mr Dog posted:i am fpgas are amazing for relatively low run stuff
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Mar 17, 2015 23:59
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fpgas make me want to drink
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Mar 18, 2015 00:48
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i have a lookup table mapping 10-bit values to 9-bit values. every possible 10 bit input is accounted for. you would think that, given absolutely arbitrary 10-bit input, it would be utterly impossible to get a 9-bit output that does not exist in the table. and yet...  in fact, it is such a frequent occurrence i can reliably trigger a scope on it.
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Mar 18, 2015 01:32
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atomicthumbs posted:from reading this thread, i am no longer interested in FPGA design spend some time working with them, then you'll really no longer be interested Bloody posted:fpgas make me want to drink same except kill myself
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Mar 18, 2015 01:50
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Bloody posted:i have a lookup table mapping 10-bit values to 9-bit values. every possible 10 bit input is accounted for. you would think that, given absolutely arbitrary 10-bit input, it would be utterly impossible to get a 9-bit output that does not exist in the table. 
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Mar 18, 2015 01:54
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Bloody posted:i have a lookup table mapping 10-bit values to 9-bit values. every possible 10 bit input is accounted for. you would think that, given absolutely arbitrary 10-bit input, it would be utterly impossible to get a 9-bit output that does not exist in the table. why are there 9bit values that aren't in the table tho
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Mar 18, 2015 02:19
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let it take 2 cycles to look up and see if it still happens
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Mar 18, 2015 02:20
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JawnV6 posted:let it take 2 cycles to look up and see if it still happens yeah this or slow the clock down maybe? i assume there is some signal that determines if its a hit and maybe its just taking longer than a clock. is it a CAM?
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Mar 18, 2015 02:39
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it's happening independent of master clock frequency over a 10x range so i don't think that's the issue - i cut master clock down a shitload in the first place because this prototype system has signal integrity issues that i'm totally not interested in dealing with right now so we're working in the couple of megahertz range this block is not doing anything special - it's a dead-simple 8b/10b block (9th bit being control character indicator), so nearly half of all codes are outright invalid. the deserializer in front of it is definitely making GBS threads the bed pretty regularly, as the decoder's decode error flag, which is raised whenever any of those invalid codes are hit, is raised pretty regularly. the baffling output is a completely invalid control character that the block's spitting out pretty reliably. tomorrow i'll be hunting for a wider logic analyzer so i can look at the output of the deserializer and the decoder at the same time  this all fuckin Just Worked in simulation dammit what's a CAM?
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Mar 18, 2015 04:25
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Bloody posted:what's a CAM? Content addressable memory
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Mar 18, 2015 04:29
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Arcsech posted:Content addressable memory oh. nah, i don't think so. synthesis seems to be spitting out a pile of logic and i'm not doing anything special otherwise
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Mar 18, 2015 05:44
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i tried to synthesize something yesterday and Xilinx just laughed in my face and said "nope" time to try cadence
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Mar 18, 2015 05:46
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hardware description languages are cool
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Mar 18, 2015 05:46
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as a general idea yes but all extant implementations no
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Mar 18, 2015 05:50
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