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Star War Sex Parrot posted:keeping this thread alive What env are you using? Atmel studio or something with WinAVR?
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Apr 18, 2015 14:04
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maniacdevnull posted:What env are you using? Atmel studio or something with WinAVR?
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Apr 20, 2015 22:51
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Star War Sex Parrot posted:Atmel studio, though I was looking at using Crosspack so I don't have to rely on a windows VM. Why not just run it natively in Windows? Is the VM just an easy way to keep it separated?
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Apr 21, 2015 01:14
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maniacdevnull posted:Why not just run it natively in Windows? Is the VM just an easy way to keep it separated?
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Apr 21, 2015 01:21
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Star War Sex Parrot posted:Because I don't need the performance gains that Boot Camp affords over the inconvenience of not being able to use my primary OS at the same time it sounds like your primary operating system may be a piece of poo poo
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Apr 21, 2015 01:22
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Bloody posted:it sounds like your primary operating system may be a piece of poo poo
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Apr 21, 2015 01:24
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Bloody posted:it sounds like your primary operating system may be a piece of poo poo My thoughts exactly
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Apr 21, 2015 12:09
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why does this pos toolchain not seem to support sysemverilog? what year is it???
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Apr 21, 2015 20:37
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Bloody posted:why does this pos toolchain not seem to support sysemverilog? what year is it??? in fpgaland it is always 1993
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Apr 21, 2015 22:56
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that explains all the tcl i guess
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Apr 22, 2015 15:43
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making good, useful test benches is hard, annoying
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Apr 22, 2015 18:35
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i am terribly afraid i did something unkind to this imx6's usb port. can't even get it to show up as a device to bootload it.
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Apr 22, 2015 18:40
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added to the list of things that are impossible to google for: an embedded linux as a usb host of another embedded device with a usb->serial bridge
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Apr 27, 2015 21:48
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Bloody posted:why does this pos toolchain not seem to support sysemverilog? what year is it??? are you a fellow Xilinx victim? i've been experimenting with synthesizable sv in vivado recently and it's actually working out p good so far. not using that many sv features yet so maybe i'll run into some bullshit idk i did notice one trivial thing that works fine in synthesis but not in xilinx's toy bullshit simulator: logic foo = bar && greeble; any attempt to combine declaration of type logic with a continuous assignment produces X till the end of time even if inputs are logic 1/0
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Apr 30, 2015 21:54
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I wonder if, 10 years from now, the FPGA environments will all be local web garbage running in an app shell and written with node.js it seems like the sort of tech backwardness the vendors would embrace, especially after the rest of the industry has moved on
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Apr 30, 2015 21:58
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eschaton posted:I wonder if, 10 years from now, the FPGA environments will all be local web garbage running in an app shell and written with node.js given that vivado is a java app, yes, this is exactly what fpga tooling will be like 10 years from now
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Apr 30, 2015 22:57
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Arcsech posted:given that vivado is a java app, yes, this is exactly what fpga tooling will be like 10 years from now  this isn't a crime in and of itself, java is a fine lang to house this sort of tooling
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May 1, 2015 00:26
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eschaton posted:I wonder if, 10 years from now, the FPGA environments will all be local web garbage running in an app shell and written with node.js cadence is offering something like that upload your verilog & test bench, they'll run it for you and you can check results on a dashboard on the one hand i'd absolutely love to chuck a random SW instance onto a new HW design and just hear back if it was a pass/fail, over here in reality i know it'd devolve into trying to debug some goofy bullshit at arm's length BobHoward posted:how do you feel about mountain view and/or satan clara
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May 1, 2015 02:10
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BobHoward posted:are you a fellow Xilinx victim? i've been experimenting with synthesizable sv in vivado recently and it's actually working out p good so far. not using that many sv features yet so maybe i'll run into some bullshit idk nope, microsemi. it's a relatively harmless tool chain but also relatively useless
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May 1, 2015 04:19
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ok, starting to dig into fabscalar, which generates parameterized superscalar cores i have an atlys2 board, had to download the old ISE to compile for it. i have dummy projects compiling, starting to feed the fabscalar stuff into it. the fpga shims aren't released yet, so my first shot at compiling it took an hour for it to figure out every bit was unnecessary and produce a .bit file with zero gates so i need that shim. before that, i ought to be able to simulate the thing. i don't have ncvlog that it's assuming, so i grabbed icarus verilog thinking it would do just fine in simulation. it's failing on a concatenation where they do an inline addition in the decoder: code:
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May 6, 2015 07:06
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JawnV6 posted:so i grabbed icarus verilog thinking it would do just fine in simulation. it's failing on a concatenation where they do an inline addition in the decoder: other than this, how are you finding Icarus Verilog? I've been planning to use it for learning this summer, but I don't want to waste my time if it's poo poo.
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May 7, 2015 09:32
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lol trick question everything is poo poo i actually did the tmp var to shave off a bit that night. a couple hours later after getting the verilog built (there were some other minor issues with it being over-pedantic) I wasn't able to get the VPI stuff compiled or linked or whatever you'd call that. tried importing the g++ built lib, tried compiling from source with the icarus VPI compiler, nothing really clicked it wouldn't be too bad starting a new design, but i'm taking a legacy code base without support and i haven't been able to recreate the simulation they did with ncvlog. I'm assuming ncvlog is the kind of tool every uni has an install kicking around so there's no need for icarus support from this particular team
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May 7, 2015 14:14
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ncvlog is the Verilog compiler from Cadence Incisive Simulator -- mega loving bucks. used it heavily for a good 4 years before switching to QuestaSim, at one point I tracked down the original firm that they assimilated into there, but don't remember what it is -- that's where the nc- prefix for all the tools comes from.
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May 7, 2015 23:17
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Bloody posted:
this loving question/problem haunts me like every two months or so and i still do not have a useful solution
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May 8, 2015 20:04
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all i want are ftdi chips and serial ports that can run, like, 10-50x faster than extant ftdi chips and serial ports why is that so much to ask for
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May 8, 2015 20:31
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no i don't want to implement a sgmii interface or whatever the hell ulpi thing for usb i just want to fart bits in one end and have them plop out the other dang it
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May 8, 2015 20:31
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Bloody posted:this loving question/problem haunts me like every two months or so and i still do not have a useful solution find a SoC that abstracts as much of that poo poo away as possible an RMII IC + Kinetis K6* series chips + their little Kinetis Design Studio thing will generate the ethernet related calls at whatever level you're comfortable with then you just be like Ethernet_SendBytes(buffer, buffer_size); there's no easy solution that doesn't have tradeoffs. option 2: become a master of the USB 2.0 spec, a curse i wish upon no one
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May 8, 2015 20:44
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serial ports can do a megabit, 10 times faster is 10baseT
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May 8, 2015 20:44
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hobbesmaster posted:serial ports can do a megabit, 10 times faster is 10baseT also true
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May 8, 2015 20:45
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hobbesmaster posted:serial ports can do a megabit, 10 times faster is 10baseT ftdi serial ports can do 10 mbit at least at burst. i need to do 20 mbps continuously, and ideally with a clear pathway towards as much as 100
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May 8, 2015 20:48
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Mido posted:find a SoC that abstracts as much of that poo poo away as possible if there are easy solutions where the tradeoff is throwing money at it, im all ears
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May 8, 2015 20:49
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Bloody posted:ftdi serial ports can do 10 mbit at least at burst. i need to do 20 mbps continuously, and ideally with a clear pathway towards as much as 100 whats the host controller
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May 8, 2015 21:19
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an fpga or fpga-containing soc. literally whatever makes this the least painful. basically there's a bunch of adcs that need to get their poo poo into a pc and those adcs are pretty quick
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May 8, 2015 21:21
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ethernet is a pretty simple protocol; http://www.fpga4fun.com/10BASE-T.html we did something like that on FPGAs in a digital logic lab in school
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May 8, 2015 21:24
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also, the cypress ez-usb fx2 or the USB3 version (creatively named fx3) owns: http://www.cypress.com/?id=193
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May 8, 2015 21:27
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hobbesmaster posted:also, the cypress ez-usb fx2 or the USB3 version (creatively named fx3) owns: http://www.cypress.com/?id=193 scanning through the fx3's info and it looks like a serious case of yes yeS yES YES, thank
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May 8, 2015 21:41
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yeah we use the fx3 for a very high frame rate camera, it legit owns. its pricey, though it sounds like you don't care about bom atm
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May 8, 2015 21:55
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someone made a Haskell-based hardware description language of some sort
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May 9, 2015 20:10
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i've got the fabscalar simulator 1 file away from working. the specific failure is: ../../libss-vpi/lib.src/misc.cc:84:3: error: C-style cast from 'char **' to 'va_list' (aka '__builtin_va_list') is not allowed so a dodgy cast in the command line parsing section of the C code being compiled to be called from the simulated HDL is why i can't get this thing built does haskell lend itself to pipelining?
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May 9, 2015 22:06
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 looks like my name is on someone's short list for good emb-c devslooks like i might soon be quoting some startup $60/hr for 2 weeks of side-job work writing some low level drivers to poll adcs on command, easy $1.5k i'll be chatting with them tomorrow about more specifics edit: yes $60/hr is really really low a cyberpunk goose fucked around with this message at 08:26 on May 10, 2015 |
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May 10, 2015 08:23
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