|
Mr. Powers posted:I think we just use the Micron M25P series with our Spartan 6's, and I've used an MT25P with a Lattice ECP5. I'm pretty sure we did something similar on older Cyclone III products, but I can't say for certain. Unless Altera is an outlier, they all pretty much comply with the standard SPI flash interface. Hm, ok -- I just got my DE0-Nano in, so I'll find out soon enough I suppose. Interested in seeing if it can boot from a FRAM SPI memory or not.
|
#
?
Feb 10, 2016 23:17
|
|
|
|
| # ? May 10, 2024 14:23 |
|
|
JawnV6 posted:From these two, it's the linker script. It's not actively being trashed by startup code, I should have more precisely stated that "every location currently assigned to RAM is trashed." code:As an aside, the signature-store cheat didn't work. Whatever weirdness is causing the watchdog hit, it seems to be affecting NV access as well. Strange.
|
|
#
?
Feb 11, 2016 01:12
|
|
|
JawnV6 posted:Linker script fix was obvious, there wasn't a .noinit section at all! After adding it in: If you just need a couple bytes, your chip might have Atmel's GPBR peripheral on it.
|
|
#
?
Feb 11, 2016 02:02
|
|
|
movax posted:Hm, ok -- I just got my DE0-Nano in, so I'll find out soon enough I suppose. Interested in seeing if it can boot from a FRAM SPI memory or not. You could always use a flash-based CPLD to push a config from FRAM if you can't directly boot! Nonvolatile configurable parts configuring configurable parts from nonvolatile memory!
|
|
#
?
Feb 12, 2016 04:09
|
|
|
sund posted:If you just need a couple bytes, your chip might have Atmel's GPBR peripheral on it. Just what I needed. Simple enough to store the task names on every entry, along with some switching on reset type I'm getting really close to figuring out why we're hitting watchdog. Thanks!
|
|
#
?
Feb 12, 2016 20:25
|
|
|
Has anyone tried pulling data off an ESP8266 over wifi to display on a webpage, or used its on-board webserver? https://www.sparkfun.com/products/13711 https://learn.sparkfun.com/tutorials/esp8266-thing-hookup-guide/example-sketch-ap-web-server I'm wondering if there's a good way to pull the data off on to an always-on linux server on the same network. Maybe using curl or wget from the server to the ESP8266 to pull the data, and once that's done the ESP8266 can delete it to free up space? What I want is for the ESP8266 to join my preexisting network and let stuff be pulled off by ssh or curl or wget, and react when that happens. I'm going to wire it up to some sensors and a battery and put it in a closet and I want to be able to get the data elsewhere on my network in an automated, command-line-friendly way, not just visit a sparsely formatted webpage on the ESP8266's own WiFi AP which would require switching networks. Edit: Also I am so in love with GNU Octave for letting me produce really nice .jpg plots with a couple lines of scripting on an embedded device. It makes it SO EASY to have a beaglebone take some sensor data, put it into a really nice bar plot, histogram, stem plot, whatever you want, and spit out a formatted .jpg or .png and then do whatever with that (like pass it in to node.js to put up on a webpage). Octave rules. reading fucked around with this message at 01:14 on Mar 4, 2016 |
|
#
?
Mar 4, 2016 01:08
|
|
|
Why don't you make the ESP8266 write to a database hosted somewhere else? https://influxdata.com/blog/how-to-send-sensor-data-to-influxdb-from-an-arduino-uno/ The ESP8266 is pushing, not the other way around.
|
|
#
?
Mar 4, 2016 05:30
|
|
|
Could anyone point me in the right direction for documentation for the Netduino 3 running .NET MF 4.3? I am really struggling trying to find any beginner's documentation that's still accurate for the most recent SDKs. Particularly stuff about steppers and PWM.
|
|
#
?
Mar 6, 2016 23:45
|
|
|
So I've crapped on the Cyclone V SoC in the past, mostly because they lost to Xilinx in getting to market first and I've been doing Zynq stuff for (gently caress me) the past 5 years or so. But, now I'm seriously thinking about dropping the Zynq, because the Cyc V has L2 ECC support in almost every L2 data store. Also, my Xilinx support sucks rear end whereas I have an Altera guy chomping at the bit to get me to switch over. The TRM is confusing as gently caress though -- the Cyc V definitely supports 1GB of RAM (max?) attached to the HPS? Is this even with ECC enabled? The Zynq tops at 1GB, 512MB if you turn on ECC. And, with 2 PCIe Hard IP blocks, which one (if any) on the Cyclone V can be used as PCIe root complex that Linux can talk too?
|
|
#
?
Mar 8, 2016 04:30
|
|
|
Does anyone have any suggestions for tools for analyzing ARM traces? There seems to be multiple different trace modules and I didn't really find a good overview of what is the difference between them and what can you do with them. This one tiny Cortex-M0+ I've been playing around has a "micro trace buffer" which AFAIK just generates a packet of source/destination address if the program counter changes non-sequentially. Then you can trigger the tracing from different watchpoints and such. If I'd like to play around with it what tools do I have on Linux for visualizing the traces? I would assume it could be possible to somehow bend gdb to my will somehow and step through the trace as a "simulation" of sorts (without knowing variable values and such though) but not sure how I'd go around doing that. I'm also interested in the more advanced trace modules (ITM, ETM) and visualizing for those too. FOSS CLI tools preferred but interested in experiences with proprietary tools as well.
|
|
#
?
Mar 25, 2016 08:33
|
|
|
I'm thinking about making an overpowered hardware accelerated switch. Can someone more knowledgeable post an outline of what I would need to buy and learn? My experience in electronics is blinking a LED with an Arduino. My electrical engineering knowledge is just this equation: V=IR. I don't remember anything else. My C programming and networking knowledge is fine though and I'm comfortable with reading the RFCs. This is an idiot spare-time project but I am OK if it costs extra.
|
|
#
?
Apr 6, 2016 22:02
|
|
|
Shinku ABOOKEN posted:I'm thinking about making an overpowered hardware accelerated switch. Can someone more knowledgeable post an outline of what I would need to buy and learn? When you say switch, I assume you mean a button or mechanism that retains an electrical state of open or closed. In which case, what are you going to accelerate? If you mean switch like an Ethernet switch, I still don't really know what you mean because most consumer switches are single chip (or close to it) dealies. I'm sick currently and my mind is cloudy right now, and those are the only two things that come to mind for what you wrote. In short, could you elaborate on what you want to do?
|
|
#
?
Apr 6, 2016 22:16
|
|
|
Shinku ABOOKEN posted:I'm thinking about making an overpowered hardware accelerated switch. Can someone more knowledgeable post an outline of what I would need to buy and learn? I think an education-oriented FPGA kit would be the way to go. I've used Digilent in the past and have been very happy with their hardware. They have extra ethernet ports (linked in the other thread) that would allow you to have several ports without having to learn any more EE. Arduino plug&play levels of electronic assembly. It's hard to offer a specific board without knowing more about your design. Maybe your budget is flexible enough to chuck $500 at something with a huge gate count & embedded ARM core. But your solution might be better served by a smaller Zynq board that would demand less of a dive into the HDL side.
|
|
#
?
Apr 6, 2016 22:31
|
|
|
Ideally I want to make a simple IP version 4 firewall. But I recognize the scope might be too much so I was thinking of starting with a layer 2 or 3 switch. I want it to be industrial grade with a bajillion bits going   .If I understand correctly the current commercial offers come with ASICs for hardware accelerated switching and routing, but those are not reprogrammable(?) so I need to use an FPGA until I have a finished design I guess(??) I really don't know where to start so any pointers are welcome. I have nobody IRL that can teach me. e: Didn't see the post above. I don't have any kind of design schematic of any sort. I was thinking of buying a board that magically had everything I needed and then stripping things I don't need. Workaday Wizard fucked around with this message at 22:57 on Apr 6, 2016 |
|
#
?
Apr 6, 2016 22:50
|
|
|
Shinku ABOOKEN posted:I really don't know where to start so any pointers are welcome. Shinku ABOOKEN posted:Ideally I want to make a simple IP version 4 firewall. But I recognize the scope might be too much so I was thinking of starting with a layer 2 or 3 switch.  Seriously, I don't know what a layer 2 or 3 switch is. Can you phrase it in terms of I/O & compute requirements? Like i'd think of my home switch as a 100MB/s full duplex on 4 ports, with maybe 20 computations done on each packet (select addressing bits, lookup routing information, determine dispatch port). e: Shinku ABOOKEN posted:e: Didn't see the post above. I don't have any kind of design schematic of any sort. I was thinking of buying a board that magically had everything I needed and then stripping things I don't need.
|
|
#
?
Apr 6, 2016 22:59
|
|
|
I think you'd probably really enjoy a capable router with an open source firmware. Trying to build from scratch what hundreds or thousands of engineers built over decades will be an exercise in futility. You might want to look at Ubiquiti or MikroTik routers as a platform. I recently bought a Ubiquiti EdgeRouter X for $60 shipped and the default firmware sounds to be pretty extensible, but not fully open. It does look like there might be an alternative open source firmware (or it might be one of the other routers that it's for). If you do want to get into more fiddly bits, the Snickerdoodle Zynq development board is supposed to have a router add-on board available. The switch would be hardware based, but all the routing would be done via the Zynq to both Ethernet and WiFi interfaces.
|
|
#
?
Apr 7, 2016 05:46
|
|
|
Use Netfpga
|
|
#
?
Apr 7, 2016 09:49
|
|
|
Figured this would be as good a place as any to ask - does anyone have any good recommendations for computer architecture books? I don't need the latest industry advances stuff, just something that will explain the basics and let me work up to designing a 1970s/80 level CPU. Patterson and Hennesey keep coming up but a lot of Amazon reviews say the books are full of errors and explain things badly. edit: also any good video lecture series Lamont fucked around with this message at 21:17 on Apr 9, 2016 |
|
#
?
Apr 9, 2016 21:13
|
|
|
Hacking the XBox is actually a surprisingly good reference, and still relevant, and free.
|
|
#
?
Apr 10, 2016 04:39
|
|
|
Patterson and Hennesey is the standard for computer architecture 101, so the negative reviews are probably just sad undergrads. I would definitely recommend it. It has tons of really good information and it is one of maybe 4 textbooks I used in undergrad that I was actually really excited to read.
|
|
#
?
Apr 10, 2016 06:37
|
|
|
Corla Plankun posted:Patterson and Hennesey is the standard for computer architecture 101, so the negative reviews are probably just sad undergrads. I would definitely recommend it. It has tons of really good information and it is one of maybe 4 textbooks I used in undergrad that I was actually really excited to read. Note that Hennesey and Patterson also exists! http://www.amazon.co.uk/Computer-Architecture-A-Quantitative-Approach/dp/1558607242 Assuming you meant http://www.amazon.co.uk/Computer-Organization-Design-Interface-Architecture/dp/0123747503
|
|
#
?
Apr 10, 2016 12:38
|
|
|
Ha! Yeah, I was talking about "Computer Organization and Design". I don't know anything about that other book.
|
|
#
?
Apr 10, 2016 19:04
|
|
|
Thanks guys, I'll give P&H a shot and see what I think of it. I'm also going to do the NAND2Tetris course as I've heard really good things about that too
|
|
#
?
Apr 11, 2016 13:52
|
|
|
movax said it was alright if I posted a dev kit I'm trying to sell in here, so here it goes. I've got a DE2i Terasic board that I opened, powered, loaded a few demos, then it went back into the box and has sat ever since. The board and peripherals are in excellent condition, and some of the stuff remained sealed. It's got a Cyclone 4 fpga with ~150k logic elements, an Intel Atom dual core cpu, 64gb ssd, wifi, switches and of course, leds. It's a large board with a ton of I/O features, and you can read up on all of them here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=529 pics: http://imgur.com/a/n9IZ5 I have loaded a demo program to test functionality before shipping. I'm asking $350 USD, which includes shipping within the US. Shipping elsewhere can be arranged but may have a slight additional fee to cover taxes and whatnot. Shoot me a pm if you're interested.
|
|
#
?
May 23, 2016 01:10
|
|
|
How can I determine that I am actually communicating with a device on the SPI bus? I know I could just read a registers expected value but that is not ideal for this situation. I am reading out a handful of registers, with unknown values but I notice that even when I disconnect my SPI clock from the devices my AVR still clocks in data on a receive and reports that everything is working correctly.
|
|
#
?
Jun 17, 2016 16:56
|
|
|
You should pull the MISO line up or down. It sounds like it might be floating, so you're getting junk data (possibly cross talk from the MOSI line) with clock disconnected. With a pull, you'll get 00 or FF if the device doesn't drive it.
|
|
#
?
Jun 17, 2016 17:09
|
|
|
If you look at the lines with a scope and/or logic analyzer, you can verify that the data you get in software matches what's on the line. If you can modify the hardware easily, you could disconnect MISO from the SPI device and watch the device's output pin with your scope/analyzer. Since it is disconnected from everything, you know any data you see there is coming from it. (Obviously the signal won't get to your uC while you are doing this test.)
|
|
#
?
Jun 17, 2016 18:28
|
|
|
Well the whole idea is that the uC is in test mode and one of the tests is verifying the SPI communications to these chips is working, well simultaneously reading data. The line is pulled low so I am clocking in all 0's but that also happens to be the same value as the data I am readingin 99% of the time. Thus I couldn't easily tell if a transaction was valid or just garbage data. I ended up just performing a read/compare of some configuration registers on each chip that have known values. Not ideal because this is a continous running test with time constraints but it'll work.
|
|
#
?
Jun 17, 2016 22:22
|
|
|
When you go into test mode, clock the bus with MISO pulled down, then clock it again with it pulled high. If you get 00 then FF, you could consider that a failure. I'm guessing you're pulling down to avoid backfeeding power to a powered down device, but if you don't have any particular attachment to pulling down, I'd just switch to a pull up.
|
|
#
?
Jun 18, 2016 02:43
|
|
|
Mr. Powers posted:When you go into test mode, clock the bus with MISO pulled down, then clock it again with it pulled high. If you get 00 then FF, you could consider that a failure. I'm guessing you're pulling down to avoid backfeeding power to a powered down device, but if you don't have any particular attachment to pulling down, I'd just switch to a pull up. Yeah this is a very power constrained project so I can't change the pulldown. Great idea though with the momentary pullup/down. I do have to continually check that the SPI bus is working well in test mode so maybe I can set it up on a timer to check the bus every second or so.
|
|
#
?
Jun 18, 2016 06:34
|
|
|
I was going to post a question about overriding GDB's thread commands to enable thread aware debugging of my FreeRTOS project without too many hacks, but it looks like Segger is adding support in their beta GDB server: https://mcuoneclipse.com/2016/06/13/adding-freertos-thread-awareness-to-gdb-and-eclipse/ I'm using a newer FreeRTOS, so I just needed to follow the instructions in the comments to ensure uxTopUsedPriority exists for the plugin. Works great!
|
|
#
?
Jun 24, 2016 19:10
|
|
|
That looks pretty nice. Better than IAR's CSPY FreeRTOS plugin, which doesn't even work for me on one of my projects because it is FreeRTOS 7.x and it's a qualified production program so I can't just upgrade the OS.
|
|
#
?
Jun 25, 2016 02:10
|
|
|
Do any of you guys work with J1939 at all? Our J1939 tooling is pretty terrible, I'd like something that makes it easier to define a J1939 network and monitor parameters/faults on the bus. I've used and really liked Vector's tools, but they're $$$$ as heck and that may be a tough sell at the moment. I'm curious if there are any other good options.
|
|
#
?
Jun 25, 2016 05:22
|
|
|
Kvaser or ATI maybe? IXAAT didn't have a horrible API, either.
|
|
#
?
Jun 27, 2016 08:39
|
|
|
So I'm getting shifted over to a project and I'll be doing the software for a MicroBlaze soft uC. Anyone have experience with this? It looks like it won't be all that different then regular uC bare metal programming but I'm curious how the build/upgrade environment works. It looks like you have to generate an XPS to configure the hardware environment, I'm assuming this is like adding peripheral busses to the uC gate logic?.
|
|
#
?
Jun 30, 2016 18:59
|
|
|
I've got a wackass embedded linux system that is logging all kinds of stuff with syslogd, which is provided through busybox. It has a line limit of 256 characters which I'm running up against. I am wondering if that limit is configurable in some way. This is the most information I've been able to get out of busybox: code:
|
|
#
?
Jun 30, 2016 23:07
|
|
|
peepsalot posted:I've got a wackass embedded linux system that is logging all kinds of stuff with syslogd, which is provided through busybox. It has a line limit of 256 characters which I'm running up against. That limit is a buffer size that is set at busybox compile time. It is option CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE, I think. You'll need to rebuild busybox with that value set higher than 256. It isn't a command line option, sorry to say.
|
|
#
?
Jul 1, 2016 02:37
|
|
|
peepsalot posted:Is there any trick to make it tell you what [OPTIONS] there are? As stated above by hendersa, you'll need to recompile busybox to change syslogd's buffer size. However in general busybox commands have a --help command line option to show their options, not -h. Alternately, there is an online interactable VM version that can be interrogated at https://busybox.net/live_bbox/live_bbox.html
|
|
#
?
Jul 1, 2016 07:07
|
|
|
This is a huge longshot, but does anyone have experience using a Beaglebone Black with OpenOCD? I've read every single English-language article I could find online and asked in all of the relevant IRC channels, but everything I found was either 'I got it working great but I'm not going to tell you how' or 'Scrub, stop being poor and use Code Composer Studio' which I even have (since I'm using an XDS100v2 adaptor that comes with a restricted license) but loathe deeply.
|
|
#
?
Aug 8, 2016 05:58
|
|
|
|
| # ? May 10, 2024 14:23 |
|
|
What are you doing that you need actual JTAG for? Normally for ARM I'd suggest getting a J-Link instead of whatever proprietary debug probe the company produces. It's supported by every embedded IDE out there or you can use the bundled GDB server, and works with anything that's a proper ARM core. To be frank I wouldn't even consider using OpenOCD unless you seriously can't afford the $60 for the edu version (non-commercial use).
|
|
#
?
Aug 9, 2016 06:09
|
|