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Combat Pretzel posted:Ryzen's achilles heel is the way the IF currently works, IMO. It really needs to go on its own clock domain. And I'm not saying that because I'm crossing my fingers that Zen 2 Threadripper will poo poo onto Intel's breakfast. If it didn't need ridiculous RAM timings it wouldn't be a problem. 3000 or 3200 isn't particularly expensive unless you need the B-die. I suspect cleaning up the IMC will be easier than un-gearing IF from the RAM clocks, and when all is said and done it gets you to the same place. I have to assume that it was engineered that way for a reason and it's not going to be as easy as internet commentators seem to think it will be.
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Dec 20, 2017 22:56
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Paul MaudDib posted:If it didn't need ridiculous RAM timings it wouldn't be a problem. 3000 or 3200 isn't particularly expensive unless you need the B-die. Come on, it can't be that hard. Just throw some FIFOs here and there and sacrifice a few more goats to Jim Keller and I'm sure it'll all work out
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Dec 21, 2017 00:33
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The ring and mesh buses over at Intel aren't tied to the RAM clock, either, and they seem to fare well, without too insane latencies. The mesh bus seems less bad than IF.
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Dec 21, 2017 01:32
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I'm cool if zen2 beats the crap out of Intel in 2019, gives me some time to enjoy the 8700K and hope the ddr memory prices start getting lower...
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Dec 21, 2017 01:37
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Ihmemies posted:I'm cool if zen2 beats the crap out of Intel in 2019, gives me some time to enjoy the 8700K and hope the ddr memory prices start getting lower... As long as their platform is stable. Like actually stable, not windows stable.
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Dec 21, 2017 02:25
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I'm just amazed were even seriously discussing AMD leaping in front of Intel at all. Also, going to bet AMD is going to be fixing their awful memory controllers across all their products, since they recently hired Mark Durcan. Not for Zen+ or Polaris 30 or whatever, but for Zen2 and Navi.
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Dec 21, 2017 02:53
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FaustianQ posted:I'm just amazed were even seriously discussing AMD leaping in front of Intel at all. please don't let navi be another spin on the GCN wheel of shame. GCN is the GPU bulldozer at this point.
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Dec 21, 2017 03:02
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By now, yes. GCN at launch was pretty decent at launch though. 28nm is a hell of a drug.
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Dec 21, 2017 03:15
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FaustianQ posted:Mark Durcan
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Dec 21, 2017 04:03
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Combat Pretzel posted:What significance does he have? He seemed to be more on the managing and process integration side of things at Micron, not actual chip design. Why need his managerial expertise then if he isn't going to oversee a revamp or significant changes in AMDs memory controller design? I mean memory controllers have always seemed to be a weak point for AMD, so I'm assuming that while they have the technical expertise necessary they lack necessary leadership? Just seems odd to nab the former Micron CEO for...reasons?
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Dec 21, 2017 04:27
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If there is one place where process integration and management is heavily needed, it's with regard to HBM2 stacks not presenting a level plane with Vega dies. (https://www.youtube.com/watch?v=mYdQNifQ7Q8&t=186s) I mention this, because this is also a very real potential problem with any CPU part with HBM stacks as well. Honestly, I don't envy the engineers who have to figure this poo poo out. At least in machining, you can always take a face mill to something or send it off to lapping. Unless they actually start building a sacrificial layer of silicon into the die stacks that they can then lap away to get everything even. But lapping on that scale is prohibitively expensive. (Another other option is, of course, to machine out islands on the heatsink or spreader cap that "reach down" to contact the HBM stacks at the same time the center surface touches die. But are we going to start matching individual heatspreaders/heatsinks to specific dies? Hell no.) So maybe we start seeing soldered heatspreaders as a matter of course on HBM parts. I dunno. Honestly, I wish I had more specific numbers on this, or a couple of sample Vega dies to measure, because as illustrative as GN's thing with ink and paper is, it doesn't actually translate to numbers. (https://www.youtube.com/watch?v=y_OgK_fUoH0) SwissArmyDruid fucked around with this message at 07:59 on Dec 21, 2017 |
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Dec 21, 2017 07:48
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Isn't the problem mostly down to one factory epoxy-coating the package and the other not? I mean, it seems like a straightforward fix to me. Do the same thing at all your factories, whether that's epoxy-fill or not. The fact that GN is finding poo poo like HBM2 stacks failing to make contact on their review samples is just laffo though, I mean gently caress guys did you even test it or did you just not pay any attention to the HBM temp sensor trying to explode through your monitor?
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Dec 21, 2017 07:59
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Epoxy coating *shouldn't* matter. If you spray a die and it adds.... like, 50 microns to the height as measured at the die, it will add roughly the same amount of thickness at the HBM stacks as well. It's not like they're masking that poo poo off... I think. I say it *shouldn't* matter, but who the gently caress hell knows when it comes to AMD and the colossal fuckup that has been HBM. I'd put this on the scale of Bulldozer in the history of AMD fuckups. Honestly, how do you get to market with HBM, only to get your legs cut out from underneath you by Micron shipping GDDR5X? Did someone just not talk to your memory suppliers? Was there a dick-waving contest involved? I bet there was a dick-waving contest involved.
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Dec 21, 2017 08:05
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SwissArmyDruid posted:I'd put this on the scale of Bulldozer in the history of AMD fuckups. Honestly, how do you get to market with HBM, only to get your legs cut out from underneath you by Micron shipping GDDR5X? Did someone just not talk to your memory suppliers? Was there a dick-waving contest involved? I bet there was a dick-waving contest involved. The thing I've heard (but don't really have a source for) is that G5X was basically invented for NVIDIA and they were financially involved in funding it, and they got a period of exclusivity as a result (much like AMD with HBM1). But, like, they could have eventually upgraded Polaris to it or something. Maybe the timing just never worked out for them. HBM1 was quite a bit before G5X, by the time it was public Polaris might have been taped out and unable to handle quad-pumped RAM, and they bet the farm on HBM2 working out with Vega. But it could easily be dick-waving contests, yeah. On that note, I dug up this article from a couple years ago and boy those predictions aged about as well as Fiji did.
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Dec 21, 2017 08:45
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SwissArmyDruid posted:it's with regard to HBM2 stacks not presenting a level plane with Vega dies. Actually changing the package or dies themselves to level out height differences probably is more trouble than its worth and would indeed be a engineering mess.
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Dec 21, 2017 08:57
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I mean they could just set specifications with reasonable tolerances and stick to them I guess.
GRINDCORE MEGGIDO fucked around with this message at 09:06 on Dec 21, 2017 |
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Dec 21, 2017 09:04
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I mean, you say that, but GDDR6 is on the horizon. Hynix and Micron have both said they'll be shipping GDDR6 early 2018. I don't think it's unreasonable to expect to see Ampere as the first mainstream GDDR6 product. AMD's continued metaphorical tripping over their own feet is putting them farther and father back behind NVidia's development cycle. (I still can't believe it's almost 2018, and Vega is still "new".) SwissArmyDruid fucked around with this message at 09:17 on Dec 21, 2017 |
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Dec 21, 2017 09:12
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GRINDCORE MEGGIDO posted:I mean they could just set specifications with reasonable tolerances and stick to them I guess. PC LOAD LETTER fucked around with this message at 09:55 on Dec 21, 2017 |
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Dec 21, 2017 09:48
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They should fill all the chips and ensure the height is consistent. Or a shim like you said. If they can't manage to sort packaging issues between a chip and hbm and suppliers, god help Navi. GRINDCORE MEGGIDO fucked around with this message at 10:27 on Dec 21, 2017 |
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Dec 21, 2017 09:53
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Guys, I want to put this number into real-world terms here: Tom's Hardware initially reported that the difference in height between HBM stacks and the Vega die was 50 microns. 50 microns/micrometers is .0019 of an inch. That is a preposterous difference to shim. This *should* be taken up by paste, but as demonstrated by GN, that difference can be much larger in other cases, to the point that the paste doesn't even adhere to the heatsink. Either way, presenting an un-even surface to the heatsink is bad juju, and the only thing that I can think of that would address such a large disparity in heights would be solder and a heatspreader. SwissArmyDruid fucked around with this message at 10:56 on Dec 21, 2017 |
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Dec 21, 2017 10:27
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Doh, of course. They really need to fill them all consistently.
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Dec 21, 2017 10:30
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Maybe do whatever Nvidia is doing with the GV100 chips? From what I've seen those are dead even.
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Dec 21, 2017 10:45
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When you're getting margins like GV100 does, BoM/production cost isn't that big an issue.
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Dec 21, 2017 14:52
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Fabs do regularly shave off the backs of dies to reduce sizes for packages, so the machinery is there.
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Dec 21, 2017 23:24
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Watermelon Daiquiri posted:Fabs do regularly shave off the backs of dies to reduce sizes for packages, so the machinery is there. They shave the backs of dies, but I'm talking about while it's on the package, shaving everything down to a uniform thickness. The machinery for THAT isn't.
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Dec 22, 2017 00:16
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Who would have thought that goons would be experts in back-shaving!? 
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Dec 22, 2017 00:23
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Paul MaudDib posted:Who would have thought that goons would be experts in back-shaving!? 
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Dec 22, 2017 00:23
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We might be seeing RAM prices come back down to a sane price next year: https://www.notebookcheck.net/Samsung-begins-mass-production-of-second-generation-10-nm-DDR4-memory.273094.0.html quote:Samsung Electronics is now enforcing its dominant position in the flash memory market by starting to mass produce the industry's first second-generation 10 nm, 8 Gb DDR4 memory chips. This happens less than two years since the introduction of the first-generation DRAM products based on the 10 nm technology, which occurred in February 2016. But I'm sure this won't hurt AMD the same way as GDDR5X, because surely AMD already has Zen+/Zen2/ZenWhatever with DDR5 memory controllers in development right now, right? ....right?
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Dec 22, 2017 02:44
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SwissArmyDruid posted:We might be seeing RAM prices come back down to a sane price next year: Dram makers didn’t use Samsung c die ram, and still use 20nm bdie chips. If they don’t adopt this new d die? ram nothing changes. Also supply is still very much constained as no new fabs are being created for dram in 2018 If you plot ddr4 ram prices alongside microns stock price I’m sure you will see similarities 
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Dec 22, 2017 02:50
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SwissArmyDruid posted:They shave the backs of dies, but I'm talking about while it's on the package, shaving everything down to a uniform thickness. The machinery for THAT isn't. oh, well, yeah, that'd defeat the entire purpose lol. But i was talking about determining the height added on the gpu dies vs all the HBM dies and shaving down the larger by the difference. a few seconds in the ol' cmp wappener.
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Dec 22, 2017 02:58
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SwissArmyDruid posted:We might be seeing RAM prices come back down to a sane price next year: Maybe we'll even get some ECC RAM.
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Dec 22, 2017 03:02
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FaustianQ posted:Why need his managerial expertise then if he isn't going to oversee a revamp or significant changes in AMDs memory controller design? I mean memory controllers have always seemed to be a weak point for AMD, so I'm assuming that while they have the technical expertise necessary they lack necessary leadership? Just seems odd to nab the former Micron CEO for...reasons?
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Dec 22, 2017 03:17
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Maybe it was some kind of esoteric deal where Micron will provide AMD with all the GDDR6 and HBM they want if only they'll take their cursed CEO.
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Dec 22, 2017 03:29
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Combat Pretzel posted:Who knows? There may be reasons we're not privvy to. Just saying, the memory controller design seems to be more a technical/design one than a managerial. I believe the Ryzen IMC is a SIP block licensed from Rambus, not an in-house design. I don't know if that means AMD isn't capable of designing one, or if maybe could do better if they shifted some resources to doing one in-house. Getting the micron guy might be a step towards that.
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Dec 22, 2017 03:45
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I remember those Samsung DDR3 ram modules were the best. They overclocked like crazy, no heatspreaders and were the cheapest around. It's about time DDR4 comes back down to normal prices.
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Dec 22, 2017 04:12
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HamHawkes posted:I remember those Samsung DDR3 ram modules were the best. They overclocked like crazy, no heatspreaders and were the cheapest around. It's about time DDR4 comes back down to normal prices. Yeah I haven't been following the prices, but I was looking for a Xeon D and some 64GB of memory, drat those prices are high. What's up with that?
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Dec 22, 2017 11:55
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Mr Shiny Pants posted:Yeah I haven't been following the prices, but I was looking for a Xeon D and some 64GB of memory, drat those prices are high. What's up with that? DDR3 stopped being made, then all DDR4 went into cellphones or something
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Dec 22, 2017 17:24
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HamHawkes posted:DDR3 stopped being made, then all DDR4 went into cellphones or something Untrue, LPDDR3 is still made in not-insignificant quantities. SwissArmyDruid fucked around with this message at 04:25 on Dec 23, 2017 |
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Dec 23, 2017 04:21
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SwissArmyDruid posted:Untrue, LPDDR3 is still made in not-insignificant quantities. Isn't that not for PC's?
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Dec 23, 2017 04:32
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You tell me if it's not for PCs, when an i5-8250U ships with dual-LPDDR3/DDR4 support. https://techreport.com/review/32863/intel-core-i5-8250u-cpu-reviewed
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Dec 23, 2017 04:38
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