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Harik posted:Unlikely to be able to exploit this via you have to not only convince it to emit the exact opcodes required to trigger it but then to somehow reveal the half of the register it wasn't using where the data was leaked. Maybe a zero-fill loop using wide registers that ends up filling with non-zero data? It'd be one hell of a talk at a security conference if someone pulls it off. There's also webasm to potentially do this. quote:e: what on earth, is there a wordfilter Khorne fucked around with this message at 18:53 on Jul 26, 2023 |
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Jul 26, 2023 18:44
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Khorne posted:Javascript could do metldown and specter. Browsers adding specific protections to stop it from happening. ahh that makes sense. meltdown and spectre were timing measurements which were patched by removing access to cycle-accurate timers from javascript. This requires you to convince javascript to (essentially) read uninitialized memory. Webassembly doesn't help you here much because it's not x86_64 assembly but an idealized virtual machine that's transpiled to the underlying platform. you'd still have to convince it to emit the exact opcodes but if you can get that reading back the leaked data is a lot more trivial.
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Jul 26, 2023 19:01
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I think the disconnect on javascript is from a security standpoint you have to assume that it's possible until mitigations are proven to stop it because people keep coming up with incredibly clever ways to pull this poo poo off. It makes sense to issue that as a warning since the impact is fairly major if achieved. There's already workarounds for non-epyc zen2 processors but they involve a larger performance hit than the microcode patch would.
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Jul 26, 2023 20:11
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https://www.reddit.com/r/Amd/comments/159xoao/stable_128gb4x32gb_ddr56000_cl30_on_agesa_1007b/ Reddit rando is reporting they can run 4x32 at DDR6000 CL30 in coupled mode on AM5 with the latest AGESA. 2DPC, 4RPC on AM5, didn't think we would see the day until Zen5. YMMV and take with a grain of salt cause of the source obvi.
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Jul 26, 2023 21:06
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Cygni posted:https://www.reddit.com/r/Amd/comments/159xoao/stable_128gb4x32gb_ddr56000_cl30_on_agesa_1007b/ I’ve got 64 more gigabytes of RAM that has been waiting for this news!
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Jul 26, 2023 21:34
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Khorne posted:Javascript could do metldown and specter. Browsers adding specific protections to stop it from happening.
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Jul 27, 2023 01:20
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pretty sure no JS implementation slowed down actual execution speed to mitigate spectre, they tackled it by making it harder to measure passage of time with high accuracy the high resolution timer API had its resolution quantized and WASM threads were disabled in shared contexts since a background thread counting in a tight loop was a good enough approximation of a high res timer
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Jul 27, 2023 01:34
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BlankSystemDaemon posted:If by specific protections you mean they slowed down JavaScript implementations so that the timings weren't tight enough to be able to do the side-channel attacks, sure. Who slowed down what?
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Jul 27, 2023 12:07
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Subjunctive posted:Who slowed down what?
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Jul 27, 2023 13:47
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Pretty much every other meltdown / spectre / retbleed mitigation has produced some performance impact, and for whatever reason javascript benchmarks are some of the most heavily affected. It's not the javascript<->VM layer that's the problem, it's the VM<->CPU level. I have the retbleed specific mitigations turned off -- retbleed has (or had at time of release) a pretty big performance loss, versus an extremely low danger for anyone but cloud / vm operators. If zenbleed mitigations also suck for performance I may just go whole hog mitigations=off and say gently caress it.
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Jul 27, 2023 15:47
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Cygni posted:Reddit rando is reporting they can run 4x32 at DDR6000 CL30 in coupled mode on AM5 with the latest AGESA. 2DPC, 4RPC on AM5, didn't think we would see the day until Zen5. YMMV and take with a grain of salt cause of the source obvi. Yeah this is the first BIOS that actually made a difference in my RAM overclocking. Not that it mattered much for me. I can get 2x 32GB sticks to DDR5 6400 stable with loosened timings and 6600 unstable with even looser timings but its still not worth going past 6000, which is where I set it back to, so its kinda cool but mostly pointless IMO unless you looking to break records. Just be aware the 1st training boot time is l o o o o n g after you change some memory settings. After that its about the same as normal though.
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Jul 27, 2023 18:05
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I can imagine that 192GB of memory can take quite a long time to train up to 6000MT/s, yeah.
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Jul 27, 2023 18:29
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Yeah the memory training is longer even when using stock expo.
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Jul 27, 2023 22:43
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I upgraded to the 58003ds and it feels very similar to my 1800x. I would not recommend. I don't think I'm getting any extra frames on my visual novel and chrome. Plus I had to press del on my computer and touch the bios to update it. Chrome still only can open 426 tabs before it starts chugging. Selling my system for a wintel rig.🤧0/10
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Jul 28, 2023 01:28
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Who are you parodying?
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Jul 28, 2023 01:33
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Dr. Video Games 0031 posted:Right, Intel still relies heavily on kernel-level scheduling, but I doubt it would perform anywhere near as well without the thread director. AMD lacks anything like that, and it's not something they can just patch in either. I know this is a necro but I think you & others have overestimated how significant Thread Director is, probably because Intel's marketing has encouraged it and tech media has mostly gone along. I read the spec once and it's just an engine to automate collection of several per-core statistics (instruction mix, current clock speed, power, temperature, etc). The resulting data can be useful to a scheduler, but the scheduler's still 100% in charge of making the actual decisions. If and when AMD does heterogeneous core types, they may not need something like this at all - Intel's need is driven by things which are probably going to remain unique to Intel. (What I'm thinking of: their overcomplicated DVFS, poorly matched core types, and use of SMT in the big cores. Speaking of SMT, when big cores are running 2 threads and those threads are competing for execution resources, making optimal scheduling decisions gets really complicated. This is probably why Intel chose to capture instruction mix.) Even if AMD ends up needing this, it ain't that complicated. Both Intel and AMD have had the raw data sources (performance counters, sensors) for a long time. The only fundamentally new thing in Thread Director is that to minimize data collection overhead, Intel threw in a tiny microcontroller core whose only job is to periodically scan performance counters and sensors and dump the data into a table for easy ingestion by the kernel.
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Jul 30, 2023 08:35
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https://www.youtube.com/watch?v=1nu-GKq58Og minisforum appears to have stepped it up. this is a really nice looking mini pc, all metal, quiet, upgradeable, but using LM in the cooler so don't open it. 2x usb4/thunderbolt allow either dock/display expansion or some interesting networking possibilities. the triangle networking (with 2-port) is a very common strategy for small clusters in general. works with 2-port enterprise ethernet adapters or infiniband adapters in homelab servers too, just direct-connect your way to success. QSFP/QSFP28 copper DAC or SFP+ copper DAC cables are cheap, as are QSFP28 to SFP+ breakout cables.
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Jul 30, 2023 09:22
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The whole "efficiency cores can't execute AVX-512" problem is the stupidest thing. It's something that could be solved in the scheduler (CPU topology discovery is a solved problem and the scheduler could just flag e-cores as not able to run anything with AVX-512 and the first time an AVX-512 instruction causes an #UD fault on an e-core the offending thread gets flagged as needing to be run on a p-core), but because people are stupid and refuse to update their operating systems, 12th and 13th gen Intel desktop processors can't do AVX-512.
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Jul 30, 2023 09:25
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People don't like Win11, which is entirely fair. Don't buy intel if you want to stay on Win10.
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Jul 30, 2023 10:21
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Kazinsal posted:The whole "efficiency cores can't execute AVX-512" problem is the stupidest thing. It's something that could be solved in the scheduler (CPU topology discovery is a solved problem and the scheduler could just flag e-cores as not able to run anything with AVX-512 and the first time an AVX-512 instruction causes an #UD fault on an e-core the offending thread gets flagged as needing to be run on a p-core), but because people are stupid and refuse to update their operating systems, 12th and 13th gen Intel desktop processors can't do AVX-512. the trouble with that approach is it would lead to weird performance cliffs where every thread ends up getting pinned to the P cores, possibly regressing performance compared to just using AVX2 and running on both the P and E cores. if any task dispatched to your work scheduler can use AVX512 then every thread in the worker pool will end up getting pinned. if your libc has AVX512 versions of common routines like memcpy then every thread will end up getting pinned. any 3rd party libraries you call might run AVX512 code and pin the calling thread without you knowing. in practice it's something that software would have to be aware of and work around, so it would be a breaking change in spirit even if the code technically runs, and if you're making a breaking change you might as well go all the way (see AVX10)
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Jul 30, 2023 12:25
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So I was like "ARM android and ios have been doing big.little for a decade, how do they handle this stuff?" And apparently the answer is that every time in that decade there was a possibility to have two cores with different instruction set compatibility, they said "gently caress no!". They ran big cores in aarch32 mode when the little cores were still 32bit. They've been doing the same thing as AVX10 (big cores run full width at full speed, little cores run half speed) since the beginning of NEON. It is kinda astonishing that Intel took that history and decided to ship the CPU the way they did. Wibla posted:People don't like Win11, which is entirely fair. Don't buy intel if you want to stay on Win10. At this point that's just a two year delay, unless you have Enterprise LTSC.
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Jul 30, 2023 14:45
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Klyith posted:At this point that's just a two year delay, unless you have Enterprise LTSC. Ridin' that train to 2032! Yeah!
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Jul 30, 2023 14:48
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Klyith posted:At this point that's just a two year delay, unless you have Enterprise LTSC. Considering how long it has taken them to unfuck the taskbar, I don't mind waiting a little longer  They're rolling out W11 to everyone at work soon, that'll be fun.
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Jul 30, 2023 14:56
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Klyith posted:They've been doing the same thing as AVX10 (big cores run full width at full speed, little cores run half speed) since the beginning of NEON. AVX10 isn't about running instructions at different rates, it's about gating the especially wide 512bit instructions so that small cores don't have to implement them at all the implication is that intel believes that 512bit operations are too heavy for E-cores even if they're decomposed into 2x256bit ops (like they did with early AVX, implemented as 2x128bit) whether due to the very large amount of register state required, or some instructions not being decomposable, or both, so presumably AVX10 on big/little chips will only support 256bit ops and AVX10 on server chips will support the optional 512bit ops.
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Jul 30, 2023 15:03
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repiv posted:AVX10 isn't about running instructions at different rates, it's about gating the especially wide 512bit instructions so that small cores don't have to implement them at all Oh, duh, it's AMD that's doing AVX512 as doubled-up 256. repiv posted:the implication is that intel believes that 512bit operations are too heavy for E-cores even if they're decomposed into 2x256bit ops (like they did with early AVX, implemented as 2x128bit) whether due to the very large amount of register state required, or some instructions not being decomposable, or both, so presumably AVX10 on big/little chips will only support 256bit ops and AVX10 on server chips will support the optional 512bit ops. Man that feels really stupid. If I make a piece of software that uses the 512bit width, how am I supposed to communicate CPU compatibility? I can't say "requires AVX10" like I could with AVX-512, it's now "requires one of this list of chips:  ". Like I know this is pretty theoretical because hardly anything uses 512 bits. But that's not going to be the case forever!For gently caress's sake, just make an E core that can run 512 even if it takes ten cycles to complete an operation and makes the E core emit an audible shrieking noise. Whatever thread is doing that will peg the E core to 100% load and get shifted to a P-core ASAP. The scheduler knows how to handle that. The most pessimistic case would be a program that infrequently uses a burst of 512 ops on an otherwise low-budget thread, but that seems... unlikely.
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Jul 30, 2023 16:07
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re-reading the announcement it's not actually clear (to me at least) whether intel is going to expose the optional 512bit mode on a per-core basis, or make it consistent across the entire chip they could make it so that a thread can execute 512bit ops only when it's running on a P-core, but that would get pretty messy so i'm not sure if they'll bother i think the 512bit mode will probably be reserved for the giant xeons that are made entirely of P cores
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Jul 30, 2023 16:34
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I suppose AMD's approach to making smaller cores by simply giving them less cache will work better for PCs, especially since AMD can glue more cache on top of them for gamer versions
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Jul 30, 2023 16:47
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FuturePastNow posted:I suppose AMD's approach to making smaller cores by simply giving them less cache will work better for PCs, especially since AMD can glue more cache on top of them for gamer versions It's not just less cache. I saw a neat article about it, a whole lot of what makes them compact is just removal of "extra" space. Some of that means that the compact cores have to run at lower frequencies, due to signal interference between components that are now closer together, and also power density. But another part is actually wasted space, because the first run of the design is more modular and "blocky" with all the various sub-components. Makes the design and fab prototyping a lot faster when you chop stuff up into highly partitioned modules. So I don't know if there will ever be an AMD CPU that uses both normal and compact at the same time. It seems likely that the C version will always be a later follow-up to the standard core, analogous to the old tick-tock cycle. The reason they can squish it down is because they've got complete understanding of how the base model worked.
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Jul 30, 2023 17:24
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Klyith posted:It's not just less cache. I saw a neat article about it, a whole lot of what makes them compact is just removal of "extra" space. Some of that means that the compact cores have to run at lower frequencies, due to signal interference between components that are now closer together, and also power density. Wendell from Level 1 seems to think that they *can* package a Zen chiplet and a ZenC chiplet together and completely sidestep all the problems that Intel has with P/E switching, and that they should largely present themselves as homogenous to the OS. https://www.youtube.com/watch?v=mquzak69LOI
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Jul 30, 2023 17:48
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SwissArmyDruid posted:Wendell from Level 1 seems to think that they *can* package a Zen chiplet and a ZenC chiplet together and completely sidestep all the problems that Intel has with P/E switching, and that they should largely present themselves as homogenous to the OS. That’d be cpu migration or cluster switching and not an HMP implementation like Intel, right?
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Jul 30, 2023 18:42
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Klyith posted:So I was like "ARM android and ios have been doing big.little for a decade, how do they handle this stuff?" samsung made big.little cores that were different enough to cause data corruption (causing crashes) because basically all the code that dealt with the relevant area assumed all cores were symmetrical this specific choice got a Linux kernel workaround I'd bet this discouraged CPU designers who saw this from trying weird poo poo like that.
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Jul 30, 2023 18:49
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hobbesmaster posted:That’d be cpu migration or cluster switching and not an HMP implementation like Intel, right? The scheduling problems might not be as bad, but any situation where you've got fast cores and slow cores creates scheduling problems. The small Zen cores might have the same instruction set but they don't clock or behave quite the same.
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Jul 30, 2023 18:50
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Twerk from Home posted:The scheduling problems might not be as bad, but any situation where you've got fast cores and slow cores creates scheduling problems. The small Zen cores might have the same instruction set but they don't clock or behave quite the same. That’s still be HMP, on ARM SoCs implementing cpu migration or cluster switching it’s treated more like dvfs states on either a per core pair or cluster basis.
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Jul 30, 2023 19:24
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repiv posted:AVX10 isn't about running instructions at different rates, it's about gating the especially wide 512bit instructions so that small cores don't have to implement them at all I was wondering if it’d be tenable to break a 512-bit operation into four 128-bit ones, which would align with Gracemont’s 4x128b ALU configuration. Something tells me the answer is “no,” that Intel instead crammed Gracemont alongside Golden Cove in a reactionary way and ran into a hard engineering issue that tanked AVX512 on the architecture. And it’s taken developing AVX10 to make it possible to salvage it. Granted, from what I’ve read as a layman it sounds like AVX512 offers advantages over SSE/AVX2 beyond the operation size, so maybe this all works out in the long term…
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Jul 30, 2023 19:32
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when intel was designing AVX they did go out of their way to structure it to enable 2x128bit implementations (most horizontal operations treat the 256bit registers as two independent 128bit banks) but i'm not sure if they made the same affordance for AVX512 to be broken down all the way to 4x128bit no matter how you divide up the compute work AVX512 still demands a huge register file though, between the doubled vector width, doubled number of registers, and extra mask registers it needs more than quadruple the scratch space that AVX did repiv fucked around with this message at 19:58 on Jul 30, 2023 |
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Jul 30, 2023 19:45
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Klyith posted:So I don't know if there will ever be an AMD CPU that uses both normal and compact at the same time. It seems likely that the C version will always be a later follow-up to the standard core, analogous to the old tick-tock cycle. The reason they can squish it down is because they've got complete understanding of how the base model worked. Strix Point, Zen5’s premium mobile part, will be a 4+8 design with Zen5/Zen5c cores and SMT enabled for all cores. It’s already been caught testing a few times. Specs could change by its 2024 launch time tho, obvi.
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Jul 30, 2023 19:53
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I think my idea of what a 7800X3D can do was a bit overstated. I want to upgrade my i7 8700 (non-k) to either a R7 7700 or a R7 7800X3D. The difference between the two on Amazon is ~$125. The local microcenter has the R7 7700 for similar prices but you can also get RAM and and a motherboard for only $100 more total (which I'd resell because I'm on ITX) In typical cases I would probably get the 7700 and call it a day, but something I've been playing a lot more of (ever since about 2016) were Paradox games. Those apparently benefit more from the X3D suffix, as do things like Dwarf Fortress and Factorio. And while it appears that they do benefit, my wonder is by exactly how much. Here's a link with simulation games benchmarks: https://www.anandtech.com/show/18795/the-amd-ryzen-7-7800x3d-review-a-simpler-slice-of-v-cache-for-gaming/4 While Factorio seemingly plays noticeably better, it looks like these tests are not necessarily made to show how much better the CPU would be in normal play. Dwarf Fortress shows that the X3D chips are better at worldgen and can shave off a decent amount of time on bigger maps, but, again im left wondering how much of anything would be felt after the worldgen.  GamersNexus shows that there's a 10% performance gap in Stellaris simulation speed between the 7700 and the 7800X3D. That seems to be significant on paper, but I'm not sure if that would actually be perceived unless you put a stopwatch on your desk and did A/B testing. There's also benchmarks floating around of Factorio ticks per second and Gonna wager that the upgrade from an i7 8700 is actually noticeable here. I guess my ask is, how much should I be considering the 7800X3D? $125 extra to this platform upgrade (especially when this is ITX and AM5 motherboards are oof) is annoying.
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Jul 30, 2023 19:53
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The 7800X3D absolutely crushes flight sims like Microsoft Flight Simulator and DCS, and it's also good with racing sims like Asseto Corsa Competizione. I agree though that there's a lack of testing around simulation games in general. And when some outlets do test those games, they don't always seem to test them properly, in the way fans of the games might want to see. I've seen a bunch of places test the frame rate in cities skylines for instance, but not the simulation speed. edit: When looking for Teardown benchmarks (couldn't find any), I found out that Star Citizen loves X3D. So... there's that. This lead me to seeking out more space sim benchmarks, and I couldn't find any benchmarks with X4 for the 7800X3D, but this post indicates that the 5800X3D offered a huge boost over the 5800X, so the 7800X3D likely offers an even bigger leap in performance. The talk in KSP forums seems to be that those games see a large benefit from X3D chips too, though I can't find any hard data to back that up. We need someone to start benchmarking Teardown by slicing the Titanic in half with a laser sword https://www.youtube.com/watch?v=LEy6xnVx5h8&t=6522s I can only guess, but I imagine this is the kind of thing that's in the wheelhouse of the X3D chips, though there probably won't a CPU for the next decade that that wouldn't chug at least a little here Dr. Video Games 0031 fucked around with this message at 20:33 on Jul 30, 2023 |
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Jul 30, 2023 20:10
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SwissArmyDruid posted:Wendell from Level 1 seems to think that they *can* package a Zen chiplet and a ZenC chiplet together and completely sidestep all the problems that Intel has with P/E switching, and that they should largely present themselves as homogenous to the OS. They definitely *can*, I was only doubtful of *will*. Particularly for standard desktop. Since the ZenC will always come a half-cycle after the main architecture, I don't think that AMD will make that combo Zen+ZenC as a desktop part. Like, it would need to be a Zen 5 performance chiplet + Zen4c efficiency chiplet. Would people want that? I mean, I guess if they want to shut down Intel on "MOAR CORES!" then a 24-core 48-thread desktop CPU is pretty much the last word. Cygni posted:Strix Point, Zen5’s premium mobile part, will be a 4+8 design with Zen5/Zen5c cores and SMT enabled for all cores. It’s already been caught testing a few times. Specs could change by its 2024 launch time tho, obvi. Yeah, that makes much more sense for mobile since that's also a half-cycle later than the lead desktop and already includes plenty of re-engineering.
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Jul 30, 2023 20:18
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Dr. Video Games 0031 posted:The 7800X3D absolutely crushes flight sims like Microsoft Flight Simulator and DCS, and it's also good with racing sims like Asseto Corsa Competizione. EDIT: To be more precise, I did three different benchmark runs with a cold boot in between, and one got 30, one got 31 and one got 32. BlankSystemDaemon fucked around with this message at 20:51 on Jul 30, 2023 |
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Jul 30, 2023 20:47
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