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BONGHITZ posted:what is lock elision? http://www.anandtech.com/show/6290/making-sense-of-intel-haswell-transactional-synchronization-extensions
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Aug 13, 2014 05:59
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pretend to grab a lock but dont do it because thats slow if someone else touches your poo poo say AW gently caress and back the gently caress up try again but sheepishly grab the lock this time
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Aug 13, 2014 06:00
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Failed Sega Accessory Ahoy!
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also hey idiot op the singular form of errata is erratum
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Aug 13, 2014 06:06
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BONGHITZ posted:so why is this tsx thing good? Luigi Thirty posted:Transactional Synchronization Extensions (TSX) is an extension to the x86 instruction set architecture that adds hardware transactional memory support, speeding up execution of multi-threaded software through lock elision. this is actually a very cool thing. basically, synchronizing threads between cores is something that saps a lot of performance. transactional memory lets a thread just try what it wants to do and if it later finds that there was a collision with another thread, that memory transaction can be discarded and the memory state rolled back so the thread can retry it. this means that if collisions are rare then there is very little synchronization overhead in most cases.
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Aug 13, 2014 06:09
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oh holy poo poo it's hardware transactional memory. i've been wondering when they would do that ever since i heard of software transactional memory. gently caress a lock imo
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Aug 13, 2014 06:10
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they're just trying to compensate for their overly strong memory model
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Aug 13, 2014 06:14
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the idea with TM is that you perform a series of transactional reads and writes, and the TM system remembers everything you saw and did. at some point you tell the system to apply the transaction, and it atomically validates all the reads and, if they check out, applies the writes. TM is all about optimistically doing a bunch of stuff and then retroactively verifying that it was okay, which in principle lets you achieve much better concurrency than using locks to prevent other threads from touching the things that you might be writing to just in case there's a conflict. the trade-off is that a thread might waste a ton of time building up a transaction only to see it cancelled. that also means there's a risk that a large transaction might never be applied because a continual stream of small transactions keeps violating its preconditions. anyway, people have been emulating this in software for awhile, but it's much more efficient to do it in hardware, which is why they were excited when Intel added hardware support, although sun had a research sparc chip with HTM years ago it's not a passive optimization for existing programs; you have to structure your code completely differently and use a bunch of new instructions
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Aug 13, 2014 06:21
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The Management posted:they're just trying to compensate for their overly strong memory model lol
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Aug 13, 2014 06:26
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theadder posted:is this still in?? what I have an i5. the best one btw. but now I have started seveloping a game and maybe an i7 would hax my compile times
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Aug 13, 2014 07:23
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ecchi when is it going early access
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Aug 13, 2014 07:35
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rjmccall posted:the idea with TM is that you perform a series of transactional reads and writes, and the TM system remembers everything you saw and did. at some point you tell the system to apply the transaction, and it atomically validates all the reads and, if they check out, applies the writes. TM is all about optimistically doing a bunch of stuff and then retroactively verifying that it was okay, which in principle lets you achieve much better concurrency than using locks to prevent other threads from touching the things that you might be writing to just in case there's a conflict. the trade-off is that a thread might waste a ton of time building up a transaction only to see it cancelled. that also means there's a risk that a large transaction might never be applied because a continual stream of small transactions keeps violating its preconditions. anyway, people have been emulating this in software for awhile, but it's much more efficient to do it in hardware, which is why they were excited when Intel added hardware support, although sun had a research sparc chip with HTM years ago iirc you only have to link against a version of glibc that uses it and use a compiler that supports it like icc v13 or gcc 4.8
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Aug 13, 2014 07:41
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Otaku Alpha Male posted:ecchi when is it going early access I've spent about 2 hours on it so very soon I guess
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Aug 13, 2014 07:51
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Sudo Echo posted:iirc you only have to link against a version of glibc that uses it and use a compiler that supports it like icc v13 or gcc 4.8 yes but if u don't code for it it's not going to take grey davatange of it is the point of it Once I read a book it was about assembler but not it was like "this is how processors actually work and so using this knowledge u can program in c efficiently or not"
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Aug 13, 2014 07:55
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echo whats your game about give me your elevator pitch
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Aug 13, 2014 09:19
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echinopsis posted:what i thought maybe was still going http://en.wikipedia.org/wiki/Intel_Upgrade_Service
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Aug 13, 2014 10:13
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lock elision lmao nice I bet that will be useful for babbies who don't already code everything lock-free
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Aug 13, 2014 10:16
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they should call them taswell cpus
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Aug 13, 2014 10:46
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Menacer posted:also hey idiot op the singular form of errata is erratum hey, i just copied the article
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Aug 13, 2014 11:00
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Otaku Alpha Male posted:echo whats your game about a side scrolling rocket/thruster game with different rocket/vehicles you can buy [which have different functions which are needed to achieve different levels requirwments] and I hope to include a quirky YOSPOS style of humour [eg idea I had was one of the characters u could be was self-diagnoses aspergers who lives in basement] and back story etc which is wack [co it's all about the gameplay but why not include hosed up story rigjt] I've made rudimentary rocket prototype and yeah I honestly feel more passionate about this project than I have about anything in my life for ages. I took need week off work even maybe to work on it? [will likely spend time doing much-overdue house chores and child things]
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Aug 13, 2014 12:13
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rock solid
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Aug 13, 2014 13:59
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Sudo Echo posted:iirc you only have to link against a version of glibc that uses it and use a compiler that supports it like icc v13 or gcc 4.8 im saying it's not like your code written with pthread_mutex_lock will magically have it's locks elides, you have to rewrite your critical sections to use the new TM apis. there might be a few builtin atomic operations that get faster because you can't otherwise do them locklessly, liking assigning to an _Atomic(struct bigger_than_two_pointers), and maybe there's some cache somewhere within glibc that benefits, but otherwise it requires user action
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Aug 13, 2014 16:31
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rjmccall posted:im saying it's not like your code written with pthread_mutex_lock will magically have it's locks elides, you have to rewrite your critical sections to use the new TM apis. there might be a few builtin atomic operations that get faster because you can't otherwise do them locklessly, liking assigning to an _Atomic(struct bigger_than_two_pointers), and maybe there's some cache somewhere within glibc that benefits, but otherwise it requires user action they're backwards compatible though, iirc. if the processor doesn't support tm, it falls back to working as an exclusive lock and i think it should be possible to use them for normal structures like hash maps? you don't want to use them for more database-style large transactional operations, i think, because it's hard to know how much memory you can use
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Aug 13, 2014 17:13
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yes, you should be able to make a very good concurrent data structure with TM, although reallocating transactions might have trouble being applied under contention. it is probably impossible to meaningfully satisfy the general STL requirements tho, so there isn't a standard concurrent map that could be silently upgraded to use TM
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Aug 13, 2014 17:30
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BONGHITZ posted:what is lock elision? isn't he that rear end in a top hat billionare who owns oracle and races yachts
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Aug 14, 2014 09:13
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~Coxy posted:isn't he that rear end in a top hat billionare who owns oracle and races yachts yup 
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Aug 14, 2014 13:57
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~Coxy posted:isn't he that rear end in a top hat billionare who owns oracle and races yachts lol
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Aug 14, 2014 16:39
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