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FPGA and microcontroller bit janitor checking in lol, just lol if you don't janitor individual bits and clock cycles
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# ¿ Dec 1, 2014 18:03 |
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# ¿ May 3, 2024 08:12 |
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eschaton posted:how many gates would an FPGA reasonably need to support to emulate a Lisp Machine CPU? I'd say one of the larger Spartan 6s would be plenty. Buy the biggest FPGA that the Webpack supports (probably either the LX45 or the LX25). The one thing that could get you is the memory - some of those LISP machines had upwards of a megabyte of RAM. Not a lot in the scheme of things, but more than a cheap FPGA will provide. So make sure you have some external memory.
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# ¿ Dec 1, 2014 18:11 |
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Bloody posted:serious q are there any non horrible ways of input fuzzing with verilog testbenches have you tried out MyHDL? It's a Python library that is designed for HDL generation - I wouldn't call it HLS or anything like that, but it's kind of like a weird mix between Python and Verilog development they have pretty good support for the Verilog VPI, so any simulators that support it (Modelsim, Icarus, probably others) will work with MyHDL. I've been messing around with using it to do unit-testing of my Verilog modules - write the module in Verilog and the testbench in MyHDL - then you get all of Python's unit-test functions and stuff. I haven't used it for unit-testing production code yet, but I've screwed around with it some and I got a testbench up and running for a counter module
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# ¿ Feb 21, 2015 22:51 |
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Bloody posted:its true. instead of using some of the new for loop constructs sysV allows, i'm writing a c# program to autogen some spaghetti code. I might be kind of retarded but what for-loop construct does sysV have that V2001 doesnt? I use for-loops in generate statements and function calls all the time and it synthesizes ok with xst Poopernickel fucked around with this message at 09:05 on Feb 25, 2015 |
# ¿ Feb 25, 2015 09:03 |
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Because im the biggest idiot on the planet, i took on the task of makefile-automating my builds with Xilinx ISE. Easy to do terribly, fucken hard as poo poo to do right Stupid pointless things done thus far: Wrote a dependency generator for ISE projects Wrote a dependency generator for EDK projects Figured out how to generate coregens on the command line to avoid putting ngcs in the repo Figured out how to conditionally set ISE parameters from the command line Killed self literally, I am a ghost now
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# ¿ Feb 25, 2015 09:10 |
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Bloody posted:i don't know what these things mean asic nerdspeak for chip-fab process variance it puts the P in PVT
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# ¿ Feb 26, 2015 18:39 |
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eschaton posted:if i were to install the Xilinx tools on Linux, would that be sufficient for new development if I just did everything through makefiles? or does the tooling really insist on an IDE-generated project file and so on, even for command-line builds? I haven't had the chance to play with Vivado yet, but if you're on 6-series FPGAs (like the Spartan 6), then you're stuck with Xilinx ISE. It's not too hard to do a pure non-IDE Makefile-based approach for simplish designs, and maybe even a coregen or two - once you start to throw EDK in the mix, it turns into waaayyy more of a clusterfuck trying to do the whole thing with a non-project flow. of course I just finished automating an ISE-based flow with Make (using xtclsh and xps -nw), and it was a pretty rough ride too so I dunno Project-based gotchas that I had to deal with: 1) Out of the box, some of the GUI tools are broken on other linuxes than RHEL6/Centos 6 - I did mine on Fedora, and I had to dick around with some library stuff to get the tools running. Some of the obscure GUI stuff still doesn't work (FPGAEditor, I'm looking at you) 2) It was a pain in the rear end to do the dependency-tracking in Make - I had to write python helper scripts to generate .d files 3) Some of the compilation steps are fundamentally grouped-output kinds of things, where one process has a bunch of dependencies and produces a pile of files. Handling that properly in Make is surprisingly hard to do robustly 4) If you're doing a project-based flow and controlling the tools with xtclsh or xps -nw, the tools sometimes want to change the timestamps on their project files even if nothing changes. My makefiles set the project files to read-only before calling the tools, and change them back afterwards edit: the silver lining is that the Linux tools really run a lot faster than their Windows equivalents Poopernickel fucked around with this message at 09:04 on Mar 2, 2015 |
# ¿ Mar 2, 2015 08:58 |
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on the bright side I learned a shitload about a bunch of make's obscure features so
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# ¿ Mar 2, 2015 09:01 |
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Bloody posted:im back to this problem (lol) with gigE you at least don't need to worry about usb drivers or any poo poo - do teh gigz
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# ¿ Mar 4, 2015 07:27 |
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octal numbers
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# ¿ Mar 7, 2015 21:33 |
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movax posted:vivado / xilinx still doesn't understand the concept of people wanting to version control stuff though. This so hard fucken drives me UP THE WALL i'm nuts-deep into automating my group's vivado flow and getting it to play nicely with source-control - holy poo poo what a colossal pain in the rear end. ISE, for all of its quirks and general shittiness, somehow easier to source-control than Vivado. also just found out that data2mem Doesn't. Even. Work. For an Artix-7 part. WHAT THE gently caress
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# ¿ Apr 6, 2015 07:24 |
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movax posted:don't even get me started on trying to version control the shitshow that's version controlling the export process over to their sdk tool as well (an eclipse-based system) I literally just got that flow working for me today - do you have any questions / are you stuck?
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# ¿ Apr 9, 2015 07:26 |
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movax posted:mostly i've got some simple parameterized modules where i want to barf if the idiot user tries to make width 0 registers or similar things You can use $finish() with Xilinx's tools to tell the synthesizer to quit. It probably works with the other guys too. Something like: code:
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# ¿ Jun 28, 2015 22:10 |
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JawnV6 posted:the synthesizer looks at those directives? thought they were simulation-only Yep! I put compile-time checks on all my parameters, especially for ones where I'm doing something clock-related like a DCM wrapper with parameterized frequency.
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# ¿ Jun 29, 2015 08:12 |
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Barnyard Protein posted:yeah dsp is awesome. what area of dsp are you interested in? i'm trying to learn it on my own, focusing on fast algorithm implementation. i wish i were in a position to go back to grad school full time, i'd do dsp. Tangent bump: This is the best book on DSP I have literally ever read - I refer back to it almost every time I need to implement something tricky: http://www.amazon.com/Understanding-Digital-Signal-Processing-Edition/dp/0137027419 What's great about it is that the book isn't academic at all. It targets the working engineer (me) who's way too lazy to digest a bunch of math just to get to a conclusion (also me) Poopernickel fucked around with this message at 20:47 on Feb 21, 2016 |
# ¿ Feb 21, 2016 20:44 |
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Sagebrush posted:pics are garbage for grognards stuck in 1995 lol, just lol if your processor's compiler costs money for a non-poo poo version GCC fo lyfe
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# ¿ May 25, 2016 21:01 |
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Microchip's Actual Website posted:
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# ¿ May 25, 2016 21:22 |
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The latest in mergergate - Qualcomm is apparently in talks to buy Xilinx
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# ¿ May 26, 2016 07:29 |
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decoupling is actually a super-complicated topic - more uFs (uF uF uF) aren't always better remember: it's not the size of the capacitor, it's how you gently caress I'd plop down a 0.1uF in the smallest package you're comfortable with, right next to each power pin. if you need ~precise~ measurements, maybe add a 1uF and an 0.01uF in parallel
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# ¿ Jan 7, 2017 01:21 |
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in tyool 2017 my employer is going into production on a brand new product, designs started from scratch in 2015 what did they pick to drive their analog knobs, leds, and buttons? an attiny88 featuring: - 512 bytes of ram - SPI controller with no FIFO and a shared data register between transmit and receive - no UART - obsolete toolchain - 8MHz clock speed - two PWM channels (and the board has 4 user-facing LEDs) - saves maybe 30 cents versus an equivalent m0, on a product that will cost several hundreds of dollars also none of the LEDs are on either of the PWM pins wish I had a hot tub time machine so I could go back and bunch that designer right in the dick Poopernickel fucked around with this message at 13:25 on May 23, 2017 |
# ¿ May 23, 2017 13:07 |
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movax posted:hahahahahaha probably a safe bet on both
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# ¿ May 23, 2017 14:23 |
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Sagebrush posted:spam spam spam For super heap big fun, try measuring your capacitance as a function of bias voltage for some kinds of caps, you can get down below half of the nominal capacitance as you get close to the rated voltage of the part. a 2.2uF/4V Y5V capacitor? On a 3.3V rail it's probably more like 1uF Poopernickel fucked around with this message at 17:38 on Jun 4, 2017 |
# ¿ Jun 4, 2017 17:34 |
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Sagebrush posted:i assume that's cause of leakage or tunneling or something as it gets closer to the breakdown voltage of the dielectric? couldn't tell you why - I love circuit design but have approximately 0% interest in the physics/chemistry aspects I do love how p. much all actual capacitors are drastically different than the 'ideal' capacitor, in surprising ways - voltage-dependance capacitance and temperature-dependent capacitance are just the tip of the fuckin iceberg
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# ¿ Jun 4, 2017 17:44 |
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just got tasked with enabling LED PWM support on the board I'm working with. this board has been through 6 revisions over the course of 2 full years. And it's basically just a poo poo microcontroller, a few knobs, and a couple of LEDs. turns out that even on the current revision, I can't use the microcontroller PWM because the only way to actually make the LED driver circuit work is to set the pin to an input and toggle the pullup resistor on and off. JESUE loving CHRIST
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# ¿ Jul 8, 2017 19:18 |
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hobbesmaster posted:can you even toggle the pullup that fast? probably not
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# ¿ Jul 8, 2017 19:23 |
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for extra lols, the LED brightness winds up depending on the value of the pullup (which goes from 50% to 200% of nominal) and also the transistor gain (which can be anywhere from 40 to 300) if the transistor gain is high enough, the circuit doesn't work at all Poopernickel fucked around with this message at 19:27 on Jul 8, 2017 |
# ¿ Jul 8, 2017 19:25 |
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only reason I can come up with for that bullshit is that they're driving it from a 3.3V micro and have to high-side switch because the LED in question is a red/green common cathode LED (it's still garbage in the worst way) also, it's a 2-channel common-cathode led (red/green) so of course they want ~*CoLoRs*~ for marketing reasons the most ironic part is that once they dial in their magic PWM value which I'll have to provide manually with timer interrupts, the colors will change wildly from unit to unit because of this poo poo circuit "constant-current source? what's that and why would we ever need it lol" Poopernickel fucked around with this message at 20:07 on Jul 8, 2017 |
# ¿ Jul 8, 2017 20:05 |
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Sagebrush posted:what were they even going for here? it's a bog-standard 5mm red/green comon cathode LED, driving it with ~15mA all of these BJTs are one-per-package SOT-23s because why place one component when you could place two instead the circuit would actually work(ish) if there was a limiting resistor between the two transistors, but as it is Q2's emitter-base current starves the LED current Poopernickel fucked around with this message at 20:14 on Jul 8, 2017 |
# ¿ Jul 8, 2017 20:08 |
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longview posted:that's pretty terrible, but you gotta admire that dedication to saving $0.001 by not putting in an extra resistor to make it work i would bet my left nut that it was an accident which stayed in the design through 6 revisions nobody ever noticed because the last firmware engineer on this project didn't know that he was toggling the pullup resistor rather than the output
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# ¿ Jul 8, 2017 20:28 |
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hobbesmaster posted:i was about to ask how but then I realized the registers are probably separated by a letter or something it's the direction register that makes the difference - On the Attiny88 and friends, the 'value' register controls the pullup resistor if the pin is an input and it's an input by default unless you set the pin to an output
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# ¿ Jul 8, 2017 20:39 |
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Sapozhnik posted:why does anybody use atmel for anything ikr
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# ¿ Jul 8, 2017 23:38 |
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Sagebrush posted:they do the job for a lot of dumb little things and unlike PIC their toolchain isn't garbage this, and also msp430's toolchain is pretty good too but in tyool 2017, there are m0+'s on the market that are on-par power-consumption wise, can compute a lot more, and are even cheaper sometimes Poopernickel fucked around with this message at 23:42 on Jul 8, 2017 |
# ¿ Jul 8, 2017 23:40 |
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ratbert90 posted:I was thinking about using a sha256 authentication chip from them. Seems cheap and would be nice for storing a private key yes? atmel is fine for that stuff, I think he meant don't gently caress wit no AVR when you can use an m0 instead
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# ¿ Jul 9, 2017 23:29 |
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Sagebrush posted:well, it's running on a cortex-m4 and i'm operating only on uint32_ts. using the mask to ensure safety for signed types makes sense. is it one cycle slower to do that, though? I'm gonna blow your mind with this poo poo: https://godbolt.org/
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# ¿ Jul 22, 2017 01:49 |
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Malcolm XML posted:What's the best PCB design software for idiot hell fuckers like me kicad if ya poor, altium if ya not i'm poor and I use kicad - it's worked for me!
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# ¿ Jul 24, 2017 16:01 |
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is ST's toolchain better than the NXP kinetis line? because hoooly poo poo it was a colossal pain to figure out how to use NXP's peripheral configurator to set up my PLLs, and the resulting code wouldn't even compile
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# ¿ Aug 2, 2017 16:10 |
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hobbesmaster posted:just use keil and cmsis i'm a poor, not gonna drop $$ for keil plus, my open sources as for cmsis, how do i get started with that shiat? is it easier/better than sperging over the processor guide and writing my own drivers for stuff?
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# ¿ Aug 3, 2017 02:53 |
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# ¿ May 3, 2024 08:12 |
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qirex posted:I saw this on an audiophile website and decided more people needed to see it i guess at that price you only need to sell one a month to book 1M in revenue
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# ¿ Aug 18, 2017 04:54 |