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pagancow posted:h.265 encoding is a serious problem, even on some of the fastest intel processors it's barely 1 fps with a single pass encode on 4+ghz quad core systems. Someone needs to up the game. sounds like u hosed up by not using the Intel Quick Sync Video hardware HEVC Main10 codec
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# ¿ Feb 12, 2017 12:25 |
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# ¿ May 4, 2024 23:16 |
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pagancow posted:lol its only 8 bits that's from 2015; kaby lake and above has 10-bit
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# ¿ Feb 12, 2017 21:00 |
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i just use lagarith to make sure i retain as much of the vhs grain and noise as possible
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# ¿ Feb 12, 2017 22:44 |
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I'm still mad about single-thread performance.
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# ¿ Feb 13, 2017 08:22 |
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Intel HD graphics four thousand achieves surprisingly high opencl performance with beignet
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# ¿ Feb 22, 2017 01:52 |
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ConanTheLibrarian posted:maybe HP will finally release their memristor-based stuff and we can ascend to the fourth level of computation lol no they gave up on "the machine" as a memristor based thing and made it some piece of linux software
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# ¿ Feb 27, 2017 03:52 |
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Fabricated posted:we use a lot of autodesk poo poo at the university I work at but i have yet to hear of any workplace that actually uses it architects use revit
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# ¿ Mar 2, 2017 05:25 |
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you'd be stupid not to take advantage of the increased bus speed tolerance you get with PCI over VLB
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# ¿ Mar 8, 2017 22:06 |
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how dense is SRAM these days and why don't we have like 32mb of L1 cache
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# ¿ Mar 10, 2017 17:25 |
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a neural network designed to validate emails
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# ¿ Mar 13, 2017 10:30 |
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Paul MaudDib posted:please, this is a solved problem yes, but you can't run the regex as a generative network to explore the multidimensional space of email addresses
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# ¿ Mar 13, 2017 22:46 |
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# ¿ Mar 16, 2017 12:41 |
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# ¿ May 4, 2024 23:16 |
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BangersInMyKnickers posted:It's a bit more complicated than that. The caches might be unified but there are four memory controllers and each core is only able to directly address two at a time. The crossbar provides the interconnect from the two halves of the processor with the two sets of memory controllers. Hitting the crossbar incurs a latency and potential bandwidth bottleneck so CoD defines the numa domains so the memory manager can attempt to avoid that when possible for everything except extremely large VMs or large/parallel workloads. I don't believe it splits L3. https://www.youtube.com/watch?v=KmtzQCSh6xk
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# ¿ Mar 22, 2017 16:17 |