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Jonny 290 posted:just make one ffs I bought a pair of alligator clamps from amazon and will clamp them to the cord stubs with a piece of cardboard between them
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Jun 17, 2015 03:35
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ah yeah my bro keeps one of those around his amp repair shop it is called cable of death
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Jun 17, 2015 04:42
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hey so if i want asserts in verilog-2001 -- what do?
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Jun 22, 2015 07:39
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do you need a little structure around $display calls or do you have the flexibility to pull in something like OVM
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Jun 22, 2015 08:08
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JawnV6 posted:do you need a little structure around $display calls or do you have the flexibility to pull in something like OVM mostly i've got some simple parameterized modules where i want to barf if the idiot user tries to make width 0 registers or similar things ovm sounds like something that'd be cool to start using though -- our stuff is so simple right now / so tiny (igloo nano fpgas) that it's not required, but i want to learn more about it
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Jun 22, 2015 08:22
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http://electronics.stackexchange.com/questions/71223/is-there-a-way-of-conditionally-triggering-a-compile-time-error-in-verilog like that?
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Jun 22, 2015 08:32
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what do verilog generators do
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Jun 27, 2015 17:16
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imagine a for loop that instantiates modules
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Jun 27, 2015 18:11
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JawnV6 posted:imagine a for loop that instantiates modules on a human face, forever
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Jun 27, 2015 20:11
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Bloody posted:what do verilog generators do You seriously have never used or even seen generators before I feel better about my ultra-poo poo FPGA skills now My pov is probably distorted because all my coworkers have been doing this poo poo for like like 30 years and are way too drat smart
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Jun 27, 2015 20:31
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Arcsech posted:You seriously have never used or even seen generators before you shouldn't have anything defined at compile time esp on a fpga I'm really curious what class of errors would be caught by the thing movax is asking for, you shouldn't be giving users too much choice. either have a template they're c/ping or don't give them the option Archsech posted:I feel better about my ultra-poo poo FPGA skills now there's no career in it, way too niche and most places just have "the fpga guy" which is why they have a fpga at all, the only people who ship fpga's on purpose is garmin, everyone else is/should actively be moving off of it
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Jun 28, 2015 08:20
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JawnV6 posted:there's no career in it, way too niche and most places just have "the fpga guy" which is why they have a fpga at all, the only people who ship fpga's on purpose is garmin, everyone else is/should actively be moving off of it We use fpgas for deep packet inspection of like 40-100gbps fiber lines and I doubt they're going away for that purpose any time soon. Still not going to make a career out of it though. Nice to be able to do though, it impresses software people who think it's black magic
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Jun 28, 2015 19:18
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Arcsech posted:it impresses software people who think it's black magic terrible metric, software folks think P=IV is magic
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Jun 28, 2015 19:27
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what's the alternative to an FPGA? serious question, everything i work with has an FPGA in it and i don't see how we realistically could do without them, we also have a lot of people in their 20s and 30s who exclusively do FPGA coding
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Jun 28, 2015 19:49
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ASICs or if you don't actually need the speed and complexity, just a microcontroller or normal processor
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Jun 28, 2015 19:58
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i guess that makes sense for high volume consumer stuff, though i'd hate to lose the ability to reflash FPGAs in the field (unless you can do that in ASICs now?)
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Jun 28, 2015 20:05
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JawnV6 posted:they're unnecessary you're going to have to define on purpose. most industrial cameras have FPGAs in them for example there's a fuckton of stuff that will not move off FPGAs because it's too low run for asics to make sense and besides the bom is small compared to the price of the product so it doesn't matter as much
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Jun 28, 2015 20:26
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does it make sense to use FPGAs to prototype an ASIC that has several different power modes and clock domains?
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Jun 28, 2015 20:30
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for every legit of those i've seen, there have been 20 where an oversized fpga is acting like a big mux between multiple MIPI paths or other situation where it's way overengineered does "industrial" translate to 10k/year volume
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Jun 28, 2015 20:31
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Barnyard Protein posted:does it make sense to use FPGAs to prototype an ASIC that has several different power modes and clock domains? FPGA's are good to prototype things in the logical domain if your power modes and clock domains might have some circuit dependencies, an FPGA is an inappropriate platform to model & mitigate those risks
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Jun 28, 2015 20:35
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hey jawn what is your opinion on this http://www.clifford.at/icestorm/ is this like the open-source synthesis equivalent of Hello World or is it closer to a Noveau-scale hardware reverse engineering accomplishment
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Jun 28, 2015 20:43
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the best application of FPGAs: the amiga-on-chip
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Jun 28, 2015 20:49
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reminds me a little of http://balboa.is/Home a lot of open source people stumble onto FPGA's and see just how awful the tooling is, but I don't think any project like that is going to get off the ground without some manufacturer support. certainly not from a cutting edge Xilinx or altera part that's really, really far along though. going from a bitstream to a verilog model is nuts, especially on what seems like a really modern product
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Jun 28, 2015 20:55
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movax posted:mostly i've got some simple parameterized modules where i want to barf if the idiot user tries to make width 0 registers or similar things You can use $finish() with Xilinx's tools to tell the synthesizer to quit. It probably works with the other guys too. Something like: code:
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Jun 28, 2015 22:10
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the synthesizer looks at those directives? thought they were simulation-only I've had hdl compilations that took 24+ hours, so the difference in compile time and cycle 1 can be huge
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Jun 29, 2015 01:53
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JawnV6 posted:the synthesizer looks at those directives? thought they were simulation-only Yep! I put compile-time checks on all my parameters, especially for ones where I'm doing something clock-related like a DCM wrapper with parameterized frequency.
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Jun 29, 2015 08:12
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Barnyard Protein posted:does it make sense to use FPGAs to prototype an ASIC that has several different power modes and clock domains? i was the fpga proto guy at prev employer. i'd take asic rtl and do what it took to get it up and running in fpga the short answer is yes long answer... you're probably not going to get much fidelity on power mode stuff without a great deal of extra effort, we didn't try putting that in fpga at all. however we did sometimes manage to keep the same clock domains in fpga as in asic, and that was valuable. as a matter of fact, this one time we collapsed 2 asic domains into 1 fpga domain we missed a bug... if you can manage to keep clocks proportional to asic you're golden. e.g., if you don't have many domains above ~500 MHz it's p reasonable to target running everything at exactly 1/10th asic rate. assuming you can make your outside interfaces behave exactly as they should, just 10x slower, you're golden this is easier said than done. the more complex the system the less likely you can do this everywhere. often the outside chips your proto has to interface to don't much like running slow. one of the difficulties for us was always dram (ddr dram DLLs don't always like operating way below their normal freq) but even without perfect clock domain modeling, many types of chip will still get a ton of value. that chip where we missed a domain crossing bug? it was a complicated soc and it was absolutely essential to have fpga prototypes, not just for validation but also as a pre-silicon software development vehicle
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Jun 29, 2015 09:12
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BobHoward posted:a pre-silicon software development vehicle yeah this is huge, having something that windows can poke at over PCIe that costs under $1k instead of starting driver development after a few million in fab costs
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Jun 29, 2015 17:20
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It'd be so nice to get to play with logic pre-silicon. oh the inputs for this module didn't get synthesized because reasons  lets do a new revision!
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Jun 29, 2015 18:54
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Fpga design sounds really fun but I have no background in it beyond doing some firmware work, how easy is it to break into?
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Jun 29, 2015 19:40
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it's addled with esoteric languages with cripplingly bad proprietary toolchains with a heaping helping of tcl smeared all over everything like poo poo on the walls of a supermax solitary cell
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Jun 29, 2015 20:28
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Also nothing you know from c programming will make sense, I spent a week making some leds flash
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Jun 29, 2015 20:35
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Mr Dog posted:Fpga design sounds really fun but I have no background in it beyond doing some firmware work, how easy is it to break into? longview posted:Also nothing you know from c programming will make sense, I spent a week making some leds flash Bloody posted:it's addled with esoteric languages with cripplingly bad proprietary toolchains with a heaping helping of tcl smeared all over everything like poo poo on the walls of a supermax solitary cell
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Jun 29, 2015 23:09
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writing hdl stuff seems like writing one level above doing npn/pnp gate layout for logical constructs (i'm p sure it is??? i still haven't written a single line of hdl-anything, if someone lays out a list of tools and a way to get started ill gladly do a hello world simulation verification thing)
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Jun 29, 2015 23:27
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vhdl is cool
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Jun 30, 2015 02:10
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i wonder if i still have access to all of the cadence stuff on campus
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Jun 30, 2015 02:13
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Star War Sex Parrot posted:vhdl is cool wrongo
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Jun 30, 2015 02:33
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JawnV6 posted:yeah this is huge, having something that windows can poke at over PCIe that costs under $1k instead of starting driver development after a few million in fab costs its even cheaper, the low-end kits from altera and xilinx with the low-end fabric + pcie hard ip + transceivers are around $500 or so i think it takes like 20 minutes to go from out-of-box to running some custom logic to make leds blink using 5 GT/s pcie, pretty legit
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Jun 30, 2015 07:38
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Mr Dog posted:Fpga design sounds really fun but I have no background in it beyond doing some firmware work, how easy is it to break into? did you ever do a 101 level digital logic class? how to build gates from transistors, how to build things from gates, k-maps, demorgan's, combinatorial vs sequential, play with 74 series chips in a hw lab, that kind of thing? you won't use much of it directly when writing fpga code but knowing it as background helps a lot if you're comfortable with firmware you can probably just crack a 101 level digital logic design textbook and learn much of what you need on your own the step after would be learning a hardware description language (hdl). the two dominant ones are vhdl and (system)verilog. they're both poo poo, in their own ways
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Jun 30, 2015 07:54
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yeah i mean i get how it works on a conceptual level, i'm just wondering how easy it would be to get a job with no prior experience.
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Jun 30, 2015 15:57
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