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did you know that 2/2 cats agree that a rubber duck wifi antenna with 3 feet of rg178 is the best toy ever
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Oct 8, 2015 05:07
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100K is a bit much for I2C pullups, isn't it? In other, TOTALLY unrelated news, TIL what an "SCR latch-up" is
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Oct 8, 2015 17:54
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single switches larger phones are cool last one I held was larger than a hockey puck
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Oct 8, 2015 18:59
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hobbesmaster posted:single switches larger phones are cool how'd you implement a markov chain in a resource constrained environment?
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Oct 8, 2015 19:06
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i know everyone's waiting with baited breath to see my choice for a binary wire encoding im liking protobuf-over-REST, theres a tiny pb in c implementation that's playing nice with my code https://github.com/nanopb/nanopb aside from optionals/repeated requiring a callback being a little goofy prepping for a presentation and playing amateur ML has been sucking up my time tho
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Oct 8, 2015 19:09
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0fc00000 13c00000 0fe0084b 0fc00000 13c00000 0fe0164c 0fc00000 13e0164c 13c00000 0fe0184d WHERE ARE THE GODDAMN HEADER/TRAILER MARKERS AFGASGASDGCXZV
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Oct 10, 2015 19:31
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Mr Dog posted:100K is a bit much for I2C pullups, isn't it? yes and lol
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Oct 12, 2015 16:44
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wasn't me who designed it (i'm the firmware guy not the hardware guy) but it was me who was told to fix the problem thankfully i had the option of asking somebody who actually knows what the gently caress when it comes to electronics i did hook up a scope to the i2c bus though and uhhhhh yeah even i could tell that something was up
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Oct 12, 2015 17:02
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the thing about i2c is that there is no magic resistor value that will always work, but 100k is insanely weak. 4k7 is a good starting point, but it might not work depending on a number of factors that would be comparatively difficult to model when you could just pick a resistor footprint, order a PCB and try it out.
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Oct 12, 2015 17:23
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1-10k will be fine basically whenever unless your doin something weird
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Oct 12, 2015 17:31
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or just use spi like a decent human being
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Oct 12, 2015 17:32
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brotherman if i was the one designing these boards then lemme tell you there is a whole heck of a lot of stuff i'd have done differently
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Oct 12, 2015 17:52
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so be the one designing them
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Oct 12, 2015 17:55
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or at least the one calling for design reviews where you browbeat the designers
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Oct 12, 2015 17:56
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the plan was 1. design some poo poo 2. hire some poor bastard (me) to actually make it work tbf it could be a lot worse (STM8 isn't ARM but at least it isn't loving Microchip and it's a lot better than AVR because it has a flat 16-bit address space) but all of this poo poo is low-volume and yet the bom cost is supposedly super important and yet there's all sorts of useless and very expensive components all over these boards. like every single one of them ships with a big chunky debug connector as opposed to idk just using pogos like a sane person. who the hell ships populated debug connectors to end users i mean wtf people. or the aforementioned 1.5F supercap which i don't even know what the gently caress it's doing there but it can't be cheap
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Oct 12, 2015 18:01
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but avr is cool and good
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Oct 12, 2015 18:12
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itym bad and fail $1 Cortex-M0 chips exist and you're still voluntarily using something with colored pointers (something something peripheral emancipation #eepromlivesmatter)
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Oct 12, 2015 18:16
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idk atmel studio is a cool and good tool and idgaf about bom
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Oct 12, 2015 18:17
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altho we are using more arm poo poo lately & ive been cursed to fpgas for the rest of eternity it seems
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Oct 12, 2015 18:18
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man you really care about what ide you're using over and above the C compiler not being a $10,000 piece of poo poo? I know AVR has a passable GCC port which is what Atmel Studio uses iirc but not all legacy micros do
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Oct 12, 2015 18:19
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its fun to do a professional googlin' and end up on avrfreaks trying to puzzle out what some arduino script kiddie did to get atmel parts to play nice
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Oct 12, 2015 18:25
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Mr Dog posted:man you really care about what ide you're using over and above the C compiler not being a $10,000 piece of poo poo? vs janitoring together my own toolchain? yeah i prefer to just run atmel studio and have poo poo work out of the box
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Oct 12, 2015 18:26
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Mr Dog posted:the plan was lol do you work with me in a slightly different alternate universe?
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Oct 12, 2015 18:32
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anybody have DDR3 layout experience? at what point are you supposed to do simulations on signal integrity? because with four memory controllers, each with 72 bit 16GB dual rank SODIMMs running at 800 MHz I think we're way past the point of "we did length matching so everything should work out of the box" . I can barely get this poo poo stable at 600 MHz and thats with pure guesswork on a billion memory controller parameters. So far I think I have found the best input terminations/output drive strengths and maybe found an address/command to clock skew issue that can be compensated for in the FPGA. but appart from a good memory test design I'm basically blind since I don't even have access to a differential probe for measurements. this Hyperlynx tool looks really neat but we don't have the money or experience for that.
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Oct 12, 2015 18:57
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not specific to that but we would've started simulating a parallel interface like that around 750 MHz ago
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Oct 13, 2015 18:22
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AUGH CLOCK DOMAINS
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Oct 19, 2015 15:10
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karasu posted:anybody have DDR3 layout experience? at what point are you supposed to do simulations on signal integrity? DDR2+ basically requires field solvers with IBIS models, there's no real way to make a good layout otherwise, using one integrated with the layout software would be the best choice since you don't have to change tools (gonna cost a good  or so)biggest wtf moment is when you realize the speed difference between outer and inner layers adds up to several centimeters length difference
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Oct 19, 2015 15:43
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longview posted:DDR2+ basically requires field solvers with IBIS models, there's no real way to make a good layout otherwise, using one integrated with the layout software would be the best choice since you don't have to change tools (gonna cost a good What our layout team did was calculate the traversal speed of the different signal layers and make a big spreadsheet which lists the lengths that each signal spends on every plane and calculate the combined delay. Then they added detours for some signals so that all the signals of a group have the same delay. We're using Altium which has signal integrity functionality but nobody used it. I joined the project when the first boards were already in the house, otherwise I would have freaked out with this workflow like our FAE did. But so far it seems to be working out, at least after a lot of trial and error with the memory controller parameters. The crucial thing to get was that most of the parameters in the memory controller do not actually influence the FPGA pins but are there for timing analysis/sign off only. I must have tried like 40 permutations of the ones that matter though like slew rate, input impedance, drive strength, clock to address delay and on chip termination at both the SODIMM and FPGA. I probably could have gotten the sweet spot of all of these much quicker with simulations rather than with 50 minute turnaround time test designs. But I have never done these simulations either. Also fitting requirements are insane for these larger FPGAs. Every time I compile I get a warning that my workstation has "only" 64 GB of ram rather than the recommended 128. Bloody posted:AUGH CLOCK DOMAINS tell me about the clock domains.
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Oct 20, 2015 12:44
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they are plentiful and crossed often
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Oct 20, 2015 12:56
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digital designers have a deep hatred of clock domain crossings. some hate them so much that they will completely ignore implementing the main feature of a module in order to not have to deal with them.
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Oct 20, 2015 14:09
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here is a halloween tip that you can try at work, instead of "BOO!" scare a digital designer by saying "CDC!"
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Oct 20, 2015 14:11
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lol idk how you would like do things without crossing a clock domain every once in a while at least mine are mostly phase locked with each other and most of my boundaries are entirely handled by IP cores
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Oct 20, 2015 14:48
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yeah i'm not a digital designer so idkwtf i'm talking about really but i work with them and they talk about CDC's like they are this insurmountable problem. stuff like - no no no we had to synchronize that async clock input because clock domain crossings.
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Oct 20, 2015 14:55
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its super fun to try debugging an issue that has a async dependency making a crossing is easy enough, gray code read/write pointers are guaranteed to settle valid. making one deterministic is ride
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Oct 20, 2015 18:21
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if you have to make it deterministic and the phases aren't at least locked you're in a lot of trouble for sure the real joy of cdc is fixing designs done by people who didn't understand cdc. production designs. that somehow kiiiinda work reliably enough to make people think it's good.  (the fix was to write all new rtl for the whole data path because gently caress fixing that, cdc was far from the only prob with it)
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Oct 20, 2015 21:11
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i have a heisenbug in my verilog gently caress fastest, most efficient course of action is probably "throw out the entire project and start over from scratch"
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Oct 20, 2015 22:38
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"throw it out and start over" is what they did for this one module that didn't work, the redesign didn't work so they threw that one out too, then they did it another time. maybe the fourth time will be different!! tbqh tho i don't think the designers are really to blame, there are other issues at play Jerry Bindle fucked around with this message at 23:23 on Oct 20, 2015 |
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Oct 20, 2015 23:19
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Bloody posted:i have a heisenbug in my verilog same but C
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Oct 20, 2015 23:26
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last time I had a fpga heisenbug it was a synthesis / optimization bug which would go away when I added logic analyzer cores connected to the problem signals. turned out this was due to my habit of slamming don't optimize constraints on signals I want to run into an analyzer (lol if u can even find what you want to look at otherwise). light dawned when I tried leaving the debug cores out and there was no prob, removed the no opt constraints and bug was back always be suspecting the toolchain
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Oct 21, 2015 01:45
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remember that time somebody autogenerated a clockless FPGA to distinguish between two tones and it had a bunch of poo poo in the corner that wasn't connected to anything and if you took that stuff out or changed the ambient temperature significantly it didn't work any more
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Oct 21, 2015 20:07
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