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eschaton posted:how bad is the stuff on OpenCores? variable it might help to calibrate your expectations that one of the biggest companies/contributors to opencores is the outfit behind kncminer
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# ? May 8, 2016 23:51 |
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# ? May 15, 2024 03:47 |
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i used a can core from them once, it was fairly decent
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# ? May 9, 2016 17:30 |
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currently planning to try getting sound output from a microcontroller. I think I'll use an msp430 to read sound data in AU format from an SD card and output everything to an external DAC welp that's the tin gang half-baked electronics project update hope you liked it
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# ? May 9, 2016 18:54 |
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Tin Gang posted:msp430 no dont
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# ? May 9, 2016 19:02 |
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also if you want an external dac then a functional block that speaks i2s is what you want
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# ? May 9, 2016 19:03 |
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au does that thing when they move stuff around to fill in empty parts of the spectrum right? like compression but not really that seems like a fun thing to implement (not) Sagebrush fucked around with this message at 19:18 on May 9, 2016 |
# ? May 9, 2016 19:09 |
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ya mean dithering?
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# ? May 9, 2016 20:52 |
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Mr Dog posted:a functional block that speaks i2s is what you want
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# ? May 9, 2016 21:06 |
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some people using some really scrub tier micros when Stm32F4 discovery boards (with built in debugger) are only $20 and have everything you need, including the ability to develop with eclipse and gcc maybe I'm biased because it's what we use at work and is by far the least awful tool chain and kit I've used for embedded work
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# ? May 9, 2016 21:07 |
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building a C simulator for riscv is taking: docker for riscv-tools plus a jdk plus scala plus sbt all of the java-ish ones are happily shuffling their versions around. i tried the native install on the latest ubuntu docker image, that wouldn't install the tools so chalk up at least one undocumented dependency.
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# ? May 9, 2016 21:11 |
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lol docker and ubuntu i'm sorry surely this stuff ought to work on grown up versions of linux like centos though. docker is extremely bad
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# ? May 9, 2016 21:17 |
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ive tried on: 1) cygwin (lol no) 2) OS X (ISA tools built fine, chisel/rocket simulator failing very early) 3) ubuntu image so far a pre-packaged riscv-tools image (by a docker engineer, not ISA wonk fwiw) is working alright, it's just clear that the chisel/rocket/fpga portions have never been run outside the berkeley campus ive used docker for tensorflow before, it's nice to have a toolchain like that not sprawling across my real machine
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# ? May 9, 2016 21:20 |
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well, install a centos image or at worst a debian image idk don't use ubuntu, so many things are pointlessly different and nothing works.
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# ? May 9, 2016 21:24 |
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DuckConference posted:some people using some really scrub tier micros when Stm32F4 discovery boards (with built in debugger) are only $20 and have everything you need, including the ability to develop with eclipse and gcc avr is least bad 8 bit uc precisely because you can just use gcc but there are steadily fewer reasons to not just arm it up as you say
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# ? May 9, 2016 21:24 |
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JawnV6 posted:ive used docker for tensorflow before, it's nice to have a toolchain like that not sprawling across my real machine docker or vagrant or anything to keep awful toolchains from making GBS threads up your host os had too many windows installs ruined by visual studio
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# ? May 9, 2016 21:27 |
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whoops, spoke too soon, make debug with known-good riscv-tools install just ended with this:code:
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# ? May 9, 2016 21:27 |
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JawnV6 posted:idk why you think centos is going to be 'better', the best clue i have is that i need "whatever OS was installed on the berkeley CS machine s141.millennium in 2014" hating ubuntu is just dog whistle racism
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# ? May 9, 2016 21:28 |
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JawnV6 posted:idk why you think centos is going to be 'better', the best clue i have is that i need "whatever OS was installed on the berkeley CS machine s141.millennium in 2014" Because Red Hat Enterprise Linux is run by grown-ups who have paying customers that get upset if you yolo your own system infrastructure for no good reason and break their poo poo in the process, and Ubuntu Linux is run by Mark Shuttleworth.
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# ? May 9, 2016 21:31 |
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the guide specifically calls out the Ubuntu packages to get, so this does feel like disconnected whistling wholly apart from my actual problem
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# ? May 9, 2016 22:19 |
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If the software stack's documentation explicitly calls out Ubuntu Linux as its preferred host environment then yes you should use that. My condolences, then.
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# ? May 9, 2016 22:24 |
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I'm getting the sense that the RISC-V guys will need some help from an adult if they want their poo poo to be used in the real world.
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# ? May 9, 2016 22:44 |
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1) all the ISA stuff is fine. if i just wanted to run linux on qemu or do SPIM-ish stuff, i've got 3 functional copies of that 2) i could recreate 90% of my advanced architecture course and i think that's the goal, running it outside the ucb eecs dept is a stretch goal
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# ? May 9, 2016 23:32 |
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looks like we've got some microcontroller designers in here? help a brother out i'm wondering how the BFI instruction is implemented in ARMv-7M MCUs. it's a bitfield insert op, any number of bits in any position in one cycle. i want the equivalent in my own design since it's very handy for the embedded stuff I'm working on. best method i came up with so far uses 3x 32-bit barrel shifters and 3x logic ops: - generate mask using lsb extending left shift: 1 <<< (field width - 1) - rotate bitfield right by field lsb - AND NOT bitfield with mask - AND input with mask - OR bitfield with input - rotate left by field lsb all well and good. but i'd rather not use three shifters if i could get away with it. it's all existing hardware in the design except for that last rotation. is there some clever trick I'm not thinking of?
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# ? May 11, 2016 15:16 |
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smask = 1 <<< (width -1) sbits = Rs & smask dmask = smask << lsb dbits = sbits << lsb Rd = rd & (!dmask) Rd = rd | dbits you need three shifts in pseudocode. one to generate the mask, one to move the mask for the destination, one to move the source bits to the destination lsb. the one that seems the most amenable to a hardware cheat is generating the mask. you could also get clever around the replacement, software has to use the correctly-shifted destination mask where you could just club the bits together and drop the original bits from Rd
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# ? May 11, 2016 18:41 |
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the fpga-targeted generated-src rocket risc-v core is something else a single 2MB .v, here's a typical section: code:
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# ? May 11, 2016 19:33 |
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mask generation w/o barrel shifters idea: use decoders and something akin to ripple carry msbi is the index of the mask msb, lsbi the index of the lsb msb_onehot = decode(msbi) lsb_onehot = decode(lsbi) now you have two bit vectors the same width as your data/mask/etc. put these through something that is structured like a ripple-carry adder. a traditional full adder cell is: assign sum = a ^ b ^ cin; assign cout = (a && b) || ((a ^ b) && cin); what you want instead is: assign sum = cin || a; assign cout = sum && !b; where the 'a' bits are connected to bits of the lsb_onehot vector, and 'b' are connected to msb_onehot. now your 'sum' contains ones starting at the lsb position and rippling up until terminated by the msb position. if you're targeting fpga, in xilinx you can take advantage of the carry chain designed for implementing adders to make this ripple carry like structure super fast, but you will have to instantiate library cells as synthesis typically won't infer the carry chain cells unless you're actually doing an addition. there's probably an equivalent way to use the carry chain in altera, but i haven't used altera in a looooonng time i would still test this against the more straightforward barrel shifter approach to make sure it is actually better. pretty sure it should be more space efficient, there might be a crossover in combinatorial delay dependent on word size
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# ? May 12, 2016 04:58 |
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you people are wizards
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# ? May 12, 2016 08:06 |
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someone recommend me a microcontroller for system monitoring. i think all i really care about is having a fuckoff lot of ADCs but i am open to many interpretations of "system monitoring" and stuff i have some default answers for this in mind but im interested to see what other people would use
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# ? May 19, 2016 14:06 |
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whatever is the least amount of effort from a sw pov (toolchains, etc) every mcu out there can do that easily how does it integrated into the system? could also get a big gently caress-off spi adc/system monitor chip and talk to it also with literally any mcu
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# ? May 20, 2016 21:29 |
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yeah, i would tend to say "whatever you already know" unless this is a hobby project and you want to learn something new for some reason like, absent all other considerations, i would say "an arduino plus the aforementioned SPI ADC" because there's nothing quicker and easier than that
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# ? May 20, 2016 21:31 |
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spankmeister posted:you people are wizards
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# ? May 22, 2016 05:08 |
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in my inbox: "microchip acquires atmel"
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# ? May 25, 2016 14:42 |
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Bloody posted:in my inbox: "microchip acquires atmel" two great tastes that go great together, imo
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# ? May 25, 2016 14:59 |
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arduino running on PIC would be awful tho
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# ? May 25, 2016 16:06 |
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pics are garbage for grognards stuck in 1995
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# ? May 25, 2016 16:11 |
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theyre good actually
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# ? May 25, 2016 20:33 |
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Sagebrush posted:pics are garbage for grognards stuck in 1995 lol, just lol if your processor's compiler costs money for a non-poo poo version GCC fo lyfe
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# ? May 25, 2016 21:01 |
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Microchip's Actual Website posted:
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# ? May 25, 2016 21:22 |
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Bloody posted:in my inbox: "microchip acquires atmel" i thought this happened last year, or is now 100% official official?
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# ? May 25, 2016 21:27 |
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# ? May 15, 2024 03:47 |
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y'know I was justing thinking about the microchip atmel thing on the way to work the other day and wasn't sure if it had every actually happened. boo
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# ? May 26, 2016 01:46 |