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Mr Dog posted:i know almost nothing about fpgas but i do know that all the fpga vendors have one guy whose job it is to come in every morning and think long and hard about everybody who keeps code for their products in any form of source control and how to loving ruin their day and then go out and do that everybody who thinks this is a joke, it is not when we asked xilinx if they could give us any guidance on which of the 27 billion files their lovely ide generates we needed to check in, we were basically told that it was silly to ask that and to go gently caress ourselves we kind of trial-and-errored out a solution but it is extremely fragile thank gently caress, im so happy i got out of fpga-land
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Aug 16, 2016 21:07
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so it wasn't just me then, lol
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Aug 17, 2016 02:01
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Arcsech posted:everybody who thinks this is a joke, it is not xilinx answered that way bc they have no clue themselves how to find out enough information to form a claim or back it up right
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Aug 17, 2016 20:32
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Barnyard Protein posted:xilinx answered that way bc they have no clue themselves how to find out enough information to form a claim or back it up right likely vivado (the xilinx ide) is a horrendous piece of poo poo in just about every way. it is the definition of software written by hardware engineers, i wouldn't be surprised if nobody really knew how it worked
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Aug 18, 2016 00:02
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what's the problem with the gui? you want autogeneration of test benches? but the tcl prompt is right there, loving pleb, why haven't you used it? 
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Aug 19, 2016 13:16
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telling people that they shouldn't want to do the thing the want to do and that the problem they have is not actually a problem is key to the business success of silicon vendors. otherwise you gotta write mad checks.
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Aug 19, 2016 18:31
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Arcsech posted:likely I've met some of the authors and they are not hardware engineers and do not pretend to be. they seemed to be reasonably cool dudes fighting understaffing, a ridiculously giant software stack, and horrible legacy issues vivado started out life as planahead, a third party tool for floor planning fpgas that was superior to xilinx's own. Xilinx bought the entire company with the idea of expanding planahead to a full suite replacement for ISE (the old ide) and several years later vivado was born. this wasn't just a gui overhaul, they also wrote entirely new synthesis and place&route tools as bad as vivado is, as much as it shows the signs of being a not-a-full-ide stretched into being one, it's still a million times better than the dogshit it replaced. and that times a million more for the back end behind the gui. also imo the worst stuff in vivado is the bad old poo poo they had to port over from ISE to keep legacy customers somewhat happy with an otherwise almost ground up toolchain rewrite. the entire "block design" infrastructure is one of those things and it's responsible for all the worst Xilinx-hates-version-control memes oh god I'm defending Xilinx tools wtf
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Aug 23, 2016 21:56
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just use chisehahahahaha
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Aug 23, 2016 22:05
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hey, found myself with some more time to work on the synth design the YMF-262 has a reset pin, but I'm not quite sure how it works. http://map.grauw.nl/resources/sound/yamaha_ymf262.pdf on the datasheet, page 17 has the timing diagrams for writing to the various pins. the diagram says to reset, set that pin to low for (for simplicity's sake) .5 of a second, right? it's actually 400 divided by the frequency of the timing signal of 14.32MHz in a standard implementation, in seconds, which is a very very small period)
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Sep 2, 2016 17:42
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generally there's only a mimumum period of time that you have to hold a reset pin low for, after that minimum time is up you can keep holding it low for as long as you want.
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Sep 2, 2016 17:44
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ok so its not just me struggling w/ blinking a loving LED in vivado. thanks red pitaya i got for free 
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Sep 2, 2016 17:48
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eschaton posted:someone please please christ i tried to learn it on altera AND xilinx and it's 100% dogshit all the way down
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Sep 2, 2016 17:52
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Mr Dog posted:generally there's only a mimumum period of time that you have to hold a reset pin low for, after that minimum time is up you can keep holding it low for as long as you want. ah ok given this is my first project, i didn't realise holding a reset pin low was, y'know, normal. Yeah i'd just hold it for a second, it's easier and it's not likely to be used a great deal. thanks mate!
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Sep 2, 2016 17:58
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hmm. Can you market programmable logic as a fashionable lifestyle product? "GAL PALs to effortlessly complement your fast-paced millennial digital lifestyle" could work
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Sep 2, 2016 17:58
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huge problem with fpgas is how much of the important poo poo is vendor locked. like ya you can use chisel or something instead of verilog but its still gotta wind up going through their dogshit synthesis flow
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Sep 2, 2016 18:10
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well that's another thing hdl synthesis isn't something that the whitest dunning-krugerest cs grad can throw together in a weekend hackfest, it's actually hard.
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Sep 2, 2016 18:21
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oh boy theres nothing like trying to bring up undocumented asics with flaky as poo poo interfaces POTENTIAL ERRATA: will draw arbitrarily large amounts of current on digital I/O if they come up with the supply; I/O have to be held low while supply comes up and cant be used for XX time after power on aka if you try to bring them up with CS/nRST high lol @ u
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Sep 8, 2016 21:17
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at least i hope thats what the problem is. maybe theyre just hosed
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Sep 8, 2016 21:18
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undocumented behavior best behavior
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Sep 8, 2016 21:23
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Bloody posted:oh boy theres nothing like trying to bring up undocumented asics with flaky as poo poo interfaces don't most large asics have power supply sequencing requirements that you have to follow in order to avoid latch-up? i know at least back in the day the TI OMAP had to have a second companion chip just to switch poo poo on in the right sequence with the right delays
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Sep 8, 2016 21:34
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professor is debating whether to have us design a 32-bit MIPS processor or an ARM one that's a 16/32-bit frankenstein monster for our semester project for the class apparently we're using verilog for it how boned am i? Apocadall fucked around with this message at 21:43 on Sep 8, 2016 |
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Sep 8, 2016 21:41
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mips is better for that
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Sep 8, 2016 21:45
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Mr Dog posted:don't most large asics have power supply sequencing requirements that you have to follow in order to avoid latch-up? i know at least back in the day the TI OMAP had to have a second companion chip just to switch poo poo on in the right sequence with the right delays a lot of people have managed to figure out how to simplify that but in this case it is a small in house single supply piece of garbage asic designed by idiots so who the hell knows
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Sep 8, 2016 21:59
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JawnV6 posted:mips is better for that i rather liked my "baby's first pipelined MIPS CPU" project in VHDL
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Sep 9, 2016 04:19
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can anybody here recommend a good cm in the united states because the one we're using now mounted a bunch of through-hole LEDs backwards on one prototype board and then dunked another prototype board with a PIR sensor on it in conformal coating
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Sep 9, 2016 17:39
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Hot Dog Day 42069 posted:yeah MIPS is definitely going to cause fewer headaches thirding this because i too enjoyed my "babby's first pipelined MIPS-ish cpu" project course back in school and "16/32 bit arm" sounds like maybe arm thumb and that's probably gonna introduce a lot of complications apocadall tell your prof to have you guys use systemverilog, not plain verilog. sv is the future (*), plain v is old and busted * where by "the future" i mean something more like "has essential quality-of-life features that should have been in verilog like 20 years ago but lol eda tools and languages are bad"
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Sep 9, 2016 18:27
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Mr Dog posted:can anybody here recommend a good cm in the united states because the one we're using now mounted a bunch of through-hole LEDs backwards on one prototype board and then dunked another prototype board with a PIR sensor on it in conformal coating BobHoward posted:thirding this because i too enjoyed my "babby's first pipelined MIPS-ish cpu" project course back in school and "16/32 bit arm" sounds like maybe arm thumb and that's probably gonna introduce a lot of complications BobHoward posted:apocadall tell your prof to have you guys use systemverilog, not plain verilog. sv is the future (*), plain v is old and busted
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Sep 9, 2016 18:36
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Mr Dog posted:don't most large asics have power supply sequencing requirements that you have to follow in order to avoid latch-up? i know at least back in the day the TI OMAP had to have a second companion chip just to switch poo poo on in the right sequence with the right delays yeah it's pretty common but it should be explicitly stated in the datasheet (where it should tell you the correct sequence and time delays)
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Sep 9, 2016 19:46
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Mr Dog posted:can anybody here recommend a good cm in the united states because the one we're using now mounted a bunch of through-hole LEDs backwards on one prototype board and then dunked another prototype board with a PIR sensor on it in conformal coating We use MVinix at work, they're in San Jose and have always been on the ball. I have no idea how much they cost though.
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Sep 9, 2016 21:28
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JawnV6 posted:thumb's awesome, but pedagogically it's a stretch to get that in and idk if it really adds value yeah. like if I was that prof I'd maybe look into risc-v if I wanted to teach with a more modern / relevant isa than 32b mips since its supposed to be "mips, but without the dumb 1980s mistakes". besides, arm thumb isn't new or very relevant since all the cool kids in the commercial world are doing 64b arm v8 also lol my phone keeps autocorrecting mips to nips
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Sep 9, 2016 21:56
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DuckConference posted:yeah it's pretty common but it should be explicitly stated in the datasheet (where it should tell you the correct sequence and time delays) lol if your in-house poo poo has a datasheet or any documentation beyond a cryptic bond diagram
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Sep 9, 2016 21:57
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gently caress verilog times a thousand but tbh sv isnt much better because tool support is dismal. langs that compile to verilog are interesting but also all broken in their own special ways - i spent all of today trying to get a chisel3 or clash or anything environment set up but with zero docs in myriad ways and/or broken ecosystem tools it has been literally impossible dehumanize and face to vhdl i guess
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Sep 9, 2016 21:58
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risc-v is about as relevant as mips in 2016 i.e. not at all so you may as well learn with risc-v because when they say risc-v they really mean mips version 5 it's basically just mips without branch delay slots or weird multiplication result registers
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Sep 9, 2016 23:22
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also dang all of a sudden i've decided that software defined radios are really goddamn cool and i want to learn more about them by which i mean learning the magical sciencey bullshit about how radios work (did i mention i write firmware for internet-of-toilets devices for a living? whatever, i fill a fifo and set a flag on one board, magic happens, i get an interrupt and drain a fifo on a different board)
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Sep 9, 2016 23:24
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*kramers thru door*
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Sep 9, 2016 23:26
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funnily enough the reason i mentioned them was because some sick madness possessed me to start reading your posts
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Sep 9, 2016 23:28
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Mr Dog posted:(did i mention i write firmware for internet-of-toilets devices for a living? whatever, i fill a fifo and set a flag on one board, magic happens, i get an interrupt and drain a fifo on a different board)
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Sep 10, 2016 02:12
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here's my linkedin spam from todayquote:Experience in a wearable or small device product development environment Jonny 290 posted:*kramers thru door* big navy boat had "DESTINATION: SEA" is there a SDR setup I could use to monitor those?
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Sep 10, 2016 02:26
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JawnV6 posted:what band are ship radios? friend of mine had a setup that would show other boats, their #'s, last port visited and any destination That's probably AIS, but my experience is limited to watching videos from an SDR king. https://www.youtube.com/watch?v=kU13FuV7IGI Edit: more obnoxious but informative video https://www.youtube.com/watch?v=-ZznkOfVivo Now I want to set up a raspberry pi and SDR to monitor ships from my house all day. Hunter2 Thompson fucked around with this message at 03:40 on Sep 10, 2016 |
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Sep 10, 2016 03:37
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http://www.rtl-sdr.com/rtl-sdr-tutorial-cheap-ais-ship-tracking/ Looks like it's doable with a $20 RTL-SDR and a good antenna.
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Sep 10, 2016 04:54
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