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Agile Vector posted:ur mum's cooter lol
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Mar 14, 2017 00:33
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omg
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Mar 14, 2017 03:20
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amd should make a javascript coprocessor
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Mar 14, 2017 04:07
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Endless Mike posted:he saw what intel could have done if only weyland-yutani hadn't gone for the lowest bidder intel does what amdon't
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Mar 14, 2017 04:56
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seeing as naples is four loving chips in one package, it would be pretty shameful if they didn't beat an e5 on speeds and feeds (not so sure about watts and dollars!)
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Mar 14, 2017 05:12
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ryzen looks surprisingly ok for naples all this poo poo hangs on their "infinity fabric," because it's four chips in one god drat can. if the interconnect sucks, naples sucks. if the interconnect rules, then... naples might be kinda sorta ok, maybe. amd has been pretty tight-lipped about the interconnect so, uh, it don't look real good
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Mar 14, 2017 05:14
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Ator posted:amd should make a javascript coprocessor every once in a while when I'm very drunk I think about this idea
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Mar 14, 2017 07:55
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Bloody posted:every once in a while when I'm very drunk I think about this idea you're very drunk more than every once in a while bloody <  >
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Mar 14, 2017 07:57
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its fun to hate on amd and all, but in general this new stuff looks like it'll be competitive enough with intel that they can play around on price, intel has huge margins, they don't need to beat them on any straight performance metric to make a bit of money
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Mar 14, 2017 09:21
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Notorious b.s.d. posted:ryzen looks surprisingly ok the core to core latency isn't that great   https://www.pcper.com/reviews/Processors/AMD-Ryzen-and-Windows-10-Scheduler-No-Silver-Bullet
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Mar 14, 2017 13:57
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Ryzen is merely not quite as good as Intel stuff which is a huge improvement from utterly comical disaster like bulldozer
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Mar 14, 2017 14:53
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Perplx posted:the core to core latency isn't that great this is latency between cores on a single chip. it is not relevant to the question. what's important for naples is the performance of the interconnect between chips. naples is literally 4x ryzen-type chips glued together. i don't mean that conceptually, or metaphorically. i mean four discrete, separated pieces of silicon glued into a single package with little wires between them. if the interconnect between chips is good, then naples will be good. if the interconnect is bad, then naples will be a turd. "infinity fabric" is the new interconnect. like hypertransport, except, AMD. if anyone sees something about "infinity fabric" pls post it here
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Mar 14, 2017 15:28
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Notorious b.s.d. posted:if anyone sees something about "infinity fabric" pls post it here 
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Mar 14, 2017 15:39
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mishaq posted:you're very drunk more than every once in a while bloody < yeah 
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Mar 14, 2017 16:43
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Notorious b.s.d. posted:"infinity fabric" is the new interconnect. like hypertransport, except, AMD. if anyone sees something about "infinity fabric" pls post it here its used in the current 8C chips- they're functionally 2 * 4C CCXs connected over that interconnect. thats what the graphs were showing, moving a thread between cores in the same CCX vs between the two CCXs thus hitting the fabric (although the graphs were trying to figure out which logical cores were the what i'm interested in is how the 2 socket systems are gonna handle big gpgpu clusters; each socket has 128 pcie lanes, but in 2 socket setups, 64 are used to provide the fabric interconnect so there's still 128 lanes leaving the sockets for the rest of the system, half from each socket
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Mar 14, 2017 17:18
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MrBadidea posted:what i'm interested in is how the 2 socket systems are gonna handle big gpgpu clusters; each socket has 128 pcie lanes, but in 2 socket setups, 64 are used to provide the fabric interconnect so there's still 128 lanes leaving the sockets for the rest of the system, half from each socket this could get kinda ugly if it's 16 pci-e lanes per chip, does that mean it's literally one gpu per chip, and moving data in/out of gpu memory requires going across the interconnect for every memory access?
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Mar 14, 2017 20:18
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Notorious b.s.d. posted:this is latency between cores on a single chip. it is not relevant to the question. what's important for naples is the performance of the interconnect between chips. the standard R7 chip (1700, 1700X, 1800X) is just a pair of dies glued together though, so Nipples will actually be 8 pieces of silicon glued together it's the same interconnect in both cases, the performance of the interconnect between a pair of dies still tells us a little about how it might perform between 8 dies - although the 5960X is not really the relevant comparison there since you'd want to look at the big quad-die E5s/E7s where the interconnect is being stressed a little harder
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Mar 15, 2017 03:53
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whats the topology
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Mar 15, 2017 08:14
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Paul MaudDib posted:the standard R7 chip (1700, 1700X, 1800X) is just a pair of dies glued together though, so Nipples will actually be 8 pieces of silicon glued together make more dies.
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Mar 15, 2017 10:26
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I CANNOT EJACULATE WITHOUT SEEING NATIVE AMERICANS BRUTALISED!
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akadajet posted:why is walter crying? because a decade ago he would have been a busty lady in skimpy clothing, or a sick rear end metallic robot-demon thing.
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Mar 15, 2017 11:17
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blowfish posted:make more dies. the bigger the better. bring back card-edge cpus
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Mar 15, 2017 13:47
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akadajet posted:why is walter crying?
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Mar 15, 2017 15:06
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Paul MaudDib posted:the standard R7 chip (1700, 1700X, 1800X) is just a pair of dies glued together though, so Nipples will actually be 8 pieces of silicon glued together the ryzen is still a single die, even if it is two "core complexes" connected by fabric on that single die i'm not sure we can infer very much from the fabric performance in the degenerate case. we don't know how many links exist on the ryzen CCXs vs a naples CCX, or what the specific topology will be with eight CCXs on four dies Paul MaudDib posted:it's the same interconnect in both cases, the performance of the interconnect between a pair of dies still tells us a little about how it might perform between 8 dies - although the 5960X is not really the relevant comparison there since you'd want to look at the big quad-die E5s/E7s where the interconnect is being stressed a little harder as far as i know all intel x86 chips are 1 die in 1 package. even the monster 22 core E5s are on a single gigantic chip. the main difference between e5 and e7 is how many qpi links you've got, which determines the possible topologies to link sockets together
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Mar 15, 2017 18:12
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Notorious b.s.d. posted:the main difference between e5 and e7 is how many qpi links you've got, 
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Mar 16, 2017 02:17
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i think anything with crystal well is 2 dies on the pcb
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Mar 16, 2017 02:19
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akadajet posted:why is walter crying? core temperature is reaching dangerous levels
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Mar 16, 2017 08:00
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Mar 16, 2017 12:41
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Perplx posted:the core to core latency isn't that great High end xeons have the same problem where the 12+ core packages are basically two 6 or 8 core packages glued together with a high speed crossbar. Software needs to be numa aware and hardware needs to present each set of cores as their own node to know not to jump the crossbar if possible or put latency insensitive things across it. It's probably ok for desktop workloads at the moment though a 4 and 4 core design is pathetic by todays standards and is going to cause a lot of headaches for programmers to optimize for. Notorious b.s.d. posted:as far as i know all intel x86 chips are 1 die in 1 package. even the monster 22 core E5s are on a single gigantic chip. Nope, they call it cluster-on-die. Intel broke out the glue gun too.
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Mar 16, 2017 14:06
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is that the german delidder guy? i mean yeah if i had infinite money i would buy a shoebox of ryzens and then go full threadripper on them because i can 
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Mar 17, 2017 02:13
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idgi why did he break the socket
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Mar 17, 2017 02:35
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A Pinball Wizard posted:idgi why did he break the socket *mounts processor in vice* *applies hammer and chisel*
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Mar 17, 2017 09:16
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BangersInMyKnickers posted:High end xeons have the same problem where the 12+ core packages are basically two 6 or 8 core packages glued together with a high speed crossbar. yes the really big xeon chips (haswell "HCC") have a funny logical layout, but i'm pretty sure they're still physically a single huge die. here is an hcc die from xeon e5 2500 v3. it's very easy to see, and count, the L2 caches for the 18 cores. (if this is actually two chips glued together, i sure don't see the seam.)  BangersInMyKnickers posted:Nope, they call it cluster-on-die. Intel broke out the glue gun too. "cluster-on-die" is a bios flag that changes l3 cache handling you can either split the big chips into two numa zones, with lower latency and crappier L3 cache performance, or you can leave them in a single pool. higher latency, better caching. Notorious b.s.d. fucked around with this message at 15:19 on Mar 17, 2017 |
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Mar 17, 2017 15:16
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It's a bit more complicated than that. The caches might be unified but there are four memory controllers and each core is only able to directly address two at a time. The crossbar provides the interconnect from the two halves of the processor with the two sets of memory controllers. Hitting the crossbar incurs a latency and potential bandwidth bottleneck so CoD defines the numa domains so the memory manager can attempt to avoid that when possible for everything except extremely large VMs or large/parallel workloads. I don't believe it splits L3.
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Mar 19, 2017 20:47
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AMD...lol! http://www.pcmag.com/news/352538/ryzen-7-chips-are-locking-up-pcs-amd-knows-why quote:AMD threw Intel a curve ball in February when the chip company announced its Ryzen CPUs would launch in early March. They are fast and significantly cheaper than Intel's equivalent Core processors. It even led to some price cuts by Intel.
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Mar 22, 2017 14:09
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Fabricated posted:AMD...lol! MAH BITS!
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Mar 22, 2017 14:42
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amd: we'll fix it in POST
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Mar 22, 2017 14:57
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infernal machines posted:amd: we'll fix it in POST
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Mar 22, 2017 15:04
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infernal machines posted:amd: we'll fix it in POST
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Mar 22, 2017 15:59
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BangersInMyKnickers posted:It's a bit more complicated than that. The caches might be unified but there are four memory controllers and each core is only able to directly address two at a time. The crossbar provides the interconnect from the two halves of the processor with the two sets of memory controllers. Hitting the crossbar incurs a latency and potential bandwidth bottleneck so CoD defines the numa domains so the memory manager can attempt to avoid that when possible for everything except extremely large VMs or large/parallel workloads. I don't believe it splits L3. https://www.youtube.com/watch?v=KmtzQCSh6xk
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Mar 22, 2017 16:17
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infernal machines posted:amd: we'll fix it in POST
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Mar 22, 2017 16:54
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