|
BobHoward posted:I wonder how much 88K Macintosh hardware is out there. I didn't know about the prototype Mac m88k HW at all, or that they even did that!
|
# ? Mar 8, 2024 01:52 |
|
|
# ? May 14, 2024 22:02 |
|
however much Mac 88k hardware is out there, 50% of it passed through Weird Stuff (RIP)
|
# ? Mar 8, 2024 01:54 |
|
Speaking of weird architectures, and since I'm not done with other would-be effortposts stuck in draft states, anyone else here other than me have any GreenArrays boards or parts?
|
# ? Mar 8, 2024 02:08 |
|
minidracula posted:From what I understand when I last looked into it, MVME was probably the most manufactured and deployed m88k form factor? Data General also originally built AViiON systems on m88k, before switching to x86 (Pentium-era, initially, I think). There were some other small scale users, OMRON's LUNA being another, mostly in Japan, and some use in telcos, etc. (Nortel had some use of m88k in some part/version/edition of DMS at one point). Beyond that I'm not sure. I know some CMU folks used m88k for some Mach projects. The sense I got was once AIM "took off" and settled on PowerPC, m88k was well and truly dead inside Motorola, and it had already had a late start compared to SPARC and MIPS in the RISC space of the era, etc., etc. If wikipedia is to be believed, m88k was a product for just 3 years, 1988 to 1991. 1991 was about when the AIM alliance formed up, and yes, PowerPC absolutely killed m88k - it hadn't gotten much adoption and PowerPC had a built-in volume customer. Take a look at this CHM history page, which is about Gary Davidian's m68k emulator projects at Apple. It has some pictures of m88k Mac hardware - a Mac LC box with the 3-chip original generation m88k stuffed in it. https://computerhistory.org/blog/transplanting-the-macs-central-processor-gary-davidian-and-his-68000-emulator/ The oral history interviews with Davidian are neat and a big chunk does concern m88k. Hard to judge from it how many 88K machines they actually built, but probably not many - sounds like the project proved itself in that 68K emulation on 88K worked well, but then the AIM deal happened and swept away any need to distribute m88k Macs to a bigger team.
|
# ? Mar 8, 2024 12:16 |
|
BobHoward posted:If wikipedia is to be believed, m88k was a product for just 3 years, 1988 to 1991. 1991 was about when the AIM alliance formed up, and yes, PowerPC absolutely killed m88k - it hadn't gotten much adoption and PowerPC had a built-in volume customer. Especially since the 601 was specifically intended to be a design replacement for the 88110, to the point of using the same bus protocol. Swap the part in your design, spin the board for the pinout, recompile/rewrite your firmware, done. Something that surprises me is that Data General switched to Intel instead of PowerPC; either they really wanted nothing more to do with Motorola or wouldn’t have anything to do with IBM, because they had a breadth of m88k designs they could have turned into 601 designs quickly. Maybe they were worried IBM would price the part to ensure no DG workstation or server was cheaper? (But IBM was still IBM then, and IBM never cared about price…)
|
# ? Mar 10, 2024 10:35 |
|
Like a buddy has an I think 8-CPU AViiON minicomputer running DG-UX with 1.5GB of RAM, and I have single-CPU tower and pizzabox AViiON workstations, and both designs would have worked with a PPC601 dropped in. They’d have been the first to market, with a decent and secure SVR4 using IXI X.desktop for its UI…
|
# ? Mar 10, 2024 10:41 |
|
it's the year of ARM on the windows desktop https://twitter.com/Lexcyn/status/1772295505524973783
|
# ? Mar 28, 2024 13:49 |
|
show me the Act 3 numbers! but yeah that’s about what I got on the Steam Deck and it’s definitely playable what’s that part go for?
|
# ? Mar 28, 2024 13:59 |
|
repiv posted:it's the year of ARM on the windows desktop Some sort of confidential arm manufacturing exclusivity contract for windows computers either expired at the end of last year or is about to expire which will allow the market to really open up
|
# ? Mar 29, 2024 09:21 |
|
I've been listening to this 2021 Twitter Spaces recording that was a retrospective / requiem for SPARC, made by a bunch of ex-Sun/Oracle people. https://www.youtube.com/watch?v=79NNXn5Kr90 It's a bit scattershot but fascinating. Lots of 'lmao our CPUs were so poo poo and doomed'. They confirmed my one of my gut reactions in a big way - I've never personally done anything with SPARC, but from a distance the register windows always looked like a terrible idea. Turns out that lots of the insiders think they were bad too.
|
# ? Apr 7, 2024 06:07 |
|
This looks very cool, though I haven’t really dug into it: https://github.com/adam-maj/tiny-gpu quote:
|
# ? Apr 26, 2024 19:29 |
|
having spoken to GPU folks on that side of the divide, it's very much a cabal dedicated to knowledge that's never written down. just the same 1000 people bouncing around 4 companies
|
# ? May 7, 2024 22:43 |
|
anyone know what sort of FPGA you need to run the CHERI implementation? thinking about making a dumb purchase
|
# ? May 7, 2024 22:59 |
Subjunctive posted:anyone know what sort of FPGA you need to run the CHERI implementation? thinking about making a dumb purchase BlankSystemDaemon fucked around with this message at 00:22 on May 8, 2024 |
|
# ? May 8, 2024 00:19 |
|
BlankSystemDaemon posted:The ARM Morello is what they're using for CheriBSD. I don’t think the ARM Morello is an FPGA, but yes that’s true.
|
# ? May 8, 2024 00:22 |
Subjunctive posted:I don’t think the ARM Morello is an FPGA, but yes that’s true.
|
|
# ? May 8, 2024 00:24 |
|
it’s OK does anyone know what kind of FPGA you need to run the CHERI implementation?
|
# ? May 8, 2024 00:26 |
Subjunctive posted:it’s OK Maybe you got a Altera Stratix 4 GX230 lying around, though? If you do, you'll need BERI.
|
|
# ? May 8, 2024 00:28 |
|
Subjunctive posted:it’s OK I think you can get away with less esp. with the smaller RISC-V BSV implementations (Piccolo, Flute), I'm trying to. We should maybe chat!(?) EDIT #1: the specific AMD/XIlinx UltraScale+ part on the board is the XCVU9P-L2FLGA2104E. EDIT #2: I'm assuming you didn't mean the CHERIoT effort (e.g., https://cheriot.org/) since you said CHERI, but just in case you did, or didn't necessarily mean to exclude it, they're building on (at least) a Diligent Arty A7-100T board (see https://cheriot.org/fpga/try/2023/11/16/cheriot-on-the-arty-a7.html && https://github.com/microsoft/cheriot-safe), specific part: XC7A100TCSG324-1. minidracula fucked around with this message at 06:32 on May 8, 2024 |
# ? May 8, 2024 06:08 |
|
There are also cheap smart NICs based on FPGAs being decommissioned by the cloud providers which you can find in ebay. Stuff like https://www.ebay.com/itm/185659756161, https://www.ebay.com/itm/144113217470 and https://www.ebay.com/itm/275258652279. Some of those FPGAs are non-standard and you'll need to use the non-free vendor tools. It's quite a rabbit hole, but some very enthusiastic enthusiast have gotten some of those to work. The altera/intel Arria parts have hard-FPUs (float32 MAC, IIRC) which can save you some resources, if you feel like integrating them into the upstream IP. This would be specially useful for implementing GPUs.
|
# ? May 8, 2024 07:33 |
|
karoshi posted:There are also cheap smart NICs based on FPGAs being decommissioned by the cloud providers which you can find in ebay. Stuff like
|
# ? May 8, 2024 07:53 |
|
Subjunctive posted:it’s OK A cheap dev kit with a Spartan 7 or Cyclone 10 will probably suffice. If you really want to be sure you'll be able to fit the core(s) you want to try... I guess e-mail someone on the CHERI team and ask for the FPGA utilization numbers? I can't find that info published anywhere, though I highly doubt they used more than a tiny fraction of that (very big and expensive) Ultrascale+ device.
|
# ? May 8, 2024 20:12 |
|
Nice, thanks all. I don’t think I can mail the CHERI folks right now without embarrassing myself, but I found a promising YouTube channel to learn the basics. https://youtube.com/@fpgasforbeginners?si=kI7Tv04zdqLcjha0
|
# ? May 8, 2024 21:21 |
|
There's this WRT PPA for a specific build of cheriot-ibex (so CHERIoT, and not any of the CHERI-RISC-V designs built on top of Piccolo, Flute, or Tooba), but I wouldn't necessarily read much into this for CHERI-RISC-V, due to a bunch of variables:quote:Timing, area and power I'm willing to bet the VCU118 is an over-provisioned board & part in general too, sure, but I guess I don't know that. I mean, it's what I'd do. Especially for multiple different core designs. And they may have been using the same board for ISAv8 and prior ISA versions and/or ARM and/or previous MIPS work. That said, I did do some very brief quick & dirty searching to see if I could turn up utilization numbers, and didn't find any re: CHERI-Piccolo, CHERI-Flute, or CHERI-Tooba, on that board/part or another, but it was a brief and very surface level search, so I'll see if I can dig up better numbers later. EDIT: OK, so I found some numbers while eating a late lunch microwaved freezer burrito: quote:Baseline Performance You'll be helped out by this PDF from 2020 <https://github.com/CTSRD-CHERI/BESSPIN-GFE/blob/cambridge/GFE_Rel5.2_System_Description.pdf> which describes the hardware in some useful ways ("GFE", here, if you're wondering, stands for "Government Furnished Equipment"). For our uses re: the table above, pp. 4-5 serve as a decoder ring to make sure we know what "P1", "P2", "P3" -- whether prefixed by either Bluespec or Chisel -- mean in context: Bluespec P1 is CHERI-Piccolo, Bluespec P2 is CHERI-Flute, Bluespec P3 is CHERI-Tooba. The same document shows what else is being instantiated on the UltraScale+ part, including supporting Xilinx IP (unsurprising). minidracula fucked around with this message at 00:13 on May 9, 2024 |
# ? May 8, 2024 23:10 |
|
minidracula posted:
Oy, that's a lot bigger than I thought (I'm used to tiny in-order ARM stuff). You're gonna need to go well above entry level to get something that can fit even the small ones. Xilinx Artix Ultrascale+ AU25P FPGA (141K LUTs, 282K regs) should be able to handle the Piccolos and mayyyyyybe the Flutes. Generally you shouldn't count on being able to go above 80% LUT/reg usage. A relatively noob-friendly Opal Kelly devkit with that FPGA will set you back about $1200. The Tooooba cores will require at least one of the larger Kintex/Virtex Ultrascale FPGAs, and those will set you back a few thousand. edit: the cheaper Artix-7 XC7A200T FPGA will probably work too, but beware of exchange rates between Ultrascale+ LUTs and 7-series LUTs. It would be nice if you had access to Vivado/Quartus so that you could do trial synthesis runs with different FPGAs and find the cheapest one that works. But if you don't have access to them through your work/school, non-locked-down licenses are not cheap Ceyton fucked around with this message at 02:24 on May 9, 2024 |
# ? May 9, 2024 02:19 |
|
|
# ? May 14, 2024 22:02 |
|
Ceyton posted:edit: the cheaper Artix-7 XC7A200T FPGA will probably work too, but beware of exchange rates between Ultrascale+ LUTs and 7-series LUTs. It would be nice if you had access to Vivado/Quartus so that you could do trial synthesis runs with different FPGAs and find the cheapest one that works. But if you don't have access to them through your work/school, non-locked-down licenses are not cheap You can generate free Vivado licenses for "WebPack" Xilinx parts, AKA the devices small and cheap enough that they don't want the cost of tools to be a barrier to people designing with them. I don't remember if the XC7A200T is a WebPack part, though. I don't think there's any significant difference between US+ and 7-series LUTs, btw? It's still a 6-input LUT architecture with roughly the same non-LUT resources. US+ routing and clock trees are much improved, though, makes timing closure much easier.
|
# ? May 9, 2024 04:02 |