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minidracula
Dec 22, 2007

boo woo boo

BobHoward posted:

I wonder how much 88K Macintosh hardware is out there.

(for those who don't know, when Apple was investigating options for transitioning away from 68K, 88K was one of them, and it got as far as them manufacturing a bunch of prototype 88K Macs for software development work.)

Actually I wonder how much 88K hardware is out there at all. Not a wildly successful ISA!
From what I understand when I last looked into it, MVME was probably the most manufactured and deployed m88k form factor? Data General also originally built AViiON systems on m88k, before switching to x86 (Pentium-era, initially, I think). There were some other small scale users, OMRON's LUNA being another, mostly in Japan, and some use in telcos, etc. (Nortel had some use of m88k in some part/version/edition of DMS at one point). Beyond that I'm not sure. I know some CMU folks used m88k for some Mach projects. The sense I got was once AIM "took off" and settled on PowerPC, m88k was well and truly dead inside Motorola, and it had already had a late start compared to SPARC and MIPS in the RISC space of the era, etc., etc.

I didn't know about the prototype Mac m88k HW at all, or that they even did that!

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Subjunctive
Sep 12, 2006

✨sparkle and shine✨

however much Mac 88k hardware is out there, 50% of it passed through Weird Stuff (RIP)

minidracula
Dec 22, 2007

boo woo boo
Speaking of weird architectures, and since I'm not done with other would-be effortposts stuck in draft states, anyone else here other than me have any GreenArrays boards or parts?

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

minidracula posted:

From what I understand when I last looked into it, MVME was probably the most manufactured and deployed m88k form factor? Data General also originally built AViiON systems on m88k, before switching to x86 (Pentium-era, initially, I think). There were some other small scale users, OMRON's LUNA being another, mostly in Japan, and some use in telcos, etc. (Nortel had some use of m88k in some part/version/edition of DMS at one point). Beyond that I'm not sure. I know some CMU folks used m88k for some Mach projects. The sense I got was once AIM "took off" and settled on PowerPC, m88k was well and truly dead inside Motorola, and it had already had a late start compared to SPARC and MIPS in the RISC space of the era, etc., etc.

I didn't know about the prototype Mac m88k HW at all, or that they even did that!

If wikipedia is to be believed, m88k was a product for just 3 years, 1988 to 1991. 1991 was about when the AIM alliance formed up, and yes, PowerPC absolutely killed m88k - it hadn't gotten much adoption and PowerPC had a built-in volume customer.

Take a look at this CHM history page, which is about Gary Davidian's m68k emulator projects at Apple. It has some pictures of m88k Mac hardware - a Mac LC box with the 3-chip original generation m88k stuffed in it.

https://computerhistory.org/blog/transplanting-the-macs-central-processor-gary-davidian-and-his-68000-emulator/

The oral history interviews with Davidian are neat and a big chunk does concern m88k. Hard to judge from it how many 88K machines they actually built, but probably not many - sounds like the project proved itself in that 68K emulation on 88K worked well, but then the AIM deal happened and swept away any need to distribute m88k Macs to a bigger team.

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?

BobHoward posted:

If wikipedia is to be believed, m88k was a product for just 3 years, 1988 to 1991. 1991 was about when the AIM alliance formed up, and yes, PowerPC absolutely killed m88k - it hadn't gotten much adoption and PowerPC had a built-in volume customer.

Especially since the 601 was specifically intended to be a design replacement for the 88110, to the point of using the same bus protocol. Swap the part in your design, spin the board for the pinout, recompile/rewrite your firmware, done.

Something that surprises me is that Data General switched to Intel instead of PowerPC; either they really wanted nothing more to do with Motorola or wouldn’t have anything to do with IBM, because they had a breadth of m88k designs they could have turned into 601 designs quickly. Maybe they were worried IBM would price the part to ensure no DG workstation or server was cheaper? (But IBM was still IBM then, and IBM never cared about price…)

eschaton
Mar 7, 2007

Don't you just hate when you wind up in a store with people who are in a socioeconomic class that is pretty obviously about two levels lower than your own?
Like a buddy has an I think 8-CPU AViiON minicomputer running DG-UX with 1.5GB of RAM, and I have single-CPU tower and pizzabox AViiON workstations, and both designs would have worked with a PPC601 dropped in. They’d have been the first to market, with a decent and secure SVR4 using IXI X.desktop for its UI…

repiv
Aug 13, 2009

it's the year of ARM on the windows desktop

https://twitter.com/Lexcyn/status/1772295505524973783

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

show me the Act 3 numbers!

but yeah that’s about what I got on the Steam Deck and it’s definitely playable

what’s that part go for?

Hadlock
Nov 9, 2004

repiv posted:

it's the year of ARM on the windows desktop

Some sort of confidential arm manufacturing exclusivity contract for windows computers either expired at the end of last year or is about to expire which will allow the market to really open up

BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull
I've been listening to this 2021 Twitter Spaces recording that was a retrospective / requiem for SPARC, made by a bunch of ex-Sun/Oracle people.

https://www.youtube.com/watch?v=79NNXn5Kr90

It's a bit scattershot but fascinating. Lots of 'lmao our CPUs were so poo poo and doomed'. They confirmed my one of my gut reactions in a big way - I've never personally done anything with SPARC, but from a distance the register windows always looked like a terrible idea. Turns out that lots of the insiders think they were bad too.

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

This looks very cool, though I haven’t really dug into it:

https://github.com/adam-maj/tiny-gpu

quote:


If you want to learn how a CPU works all the way from architecture to control signals, there are many resources online to help you.

GPUs are not the same.

Because the GPU market is so competitive, low-level technical details for all modern architectures remain proprietary.

While there are lots of resources to learn about GPU programming, there's almost nothing available to learn about how GPU's work at a hardware level.

The best option is to go through open-source GPU implementations like Miaow and VeriGPU and try to figure out what's going on. This is challenging since these projects aim at being feature complete and functional, so they're quite complex.

This is why I built tiny-gpu!

JawnV6
Jul 4, 2004

So hot ...
having spoken to GPU folks on that side of the divide, it's very much a cabal dedicated to knowledge that's never written down. just the same 1000 people bouncing around 4 companies

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

anyone know what sort of FPGA you need to run the CHERI implementation? thinking about making a dumb purchase

BlankSystemDaemon
Mar 13, 2009



Subjunctive posted:

anyone know what sort of FPGA you need to run the CHERI implementation? thinking about making a dumb purchase
The ARM Morello is what they're using for CheriBSD, and is available here. There's also a simulation available for free.

BlankSystemDaemon fucked around with this message at 00:22 on May 8, 2024

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

BlankSystemDaemon posted:

The ARM Morello is what they're using for CheriBSD.

I don’t think the ARM Morello is an FPGA, but yes that’s true.

BlankSystemDaemon
Mar 13, 2009



Subjunctive posted:

I don’t think the ARM Morello is an FPGA, but yes that’s true.
Oh, yeah it's just an ARM processor based on the Neoverse N1 with CHERI extensions - I just forgot to include the links to get it in my post, so I've edited them in.

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

it’s OK

does anyone know what kind of FPGA you need to run the CHERI implementation?

BlankSystemDaemon
Mar 13, 2009



Subjunctive posted:

it’s OK

does anyone know what kind of FPGA you need to run the CHERI implementation?
I linked the ARM Morello board, because unironically it's probably easier to get ahold of than the Terasic DE4, which is almost $6000.
Maybe you got a Altera Stratix 4 GX230 lying around, though? If you do, you'll need BERI.

minidracula
Dec 22, 2007

boo woo boo

Subjunctive posted:

it’s OK

does anyone know what kind of FPGA you need to run the CHERI implementation?
VCU118 IIRC is what they used as the dev board for CHERI ISAv9 CHERI-RISC-V implementations (CHERI-Piccolo, CHERI-Flute, and CHERI-Toooba), see: https://www.xilinx.com/products/boards-and-kits/vcu118.html

I think you can get away with less esp. with the smaller RISC-V BSV implementations (Piccolo, Flute), I'm trying to. We should maybe chat!(?)

EDIT #1: the specific AMD/XIlinx UltraScale+ part on the board is the XCVU9P-L2FLGA2104E.

EDIT #2: I'm assuming you didn't mean the CHERIoT effort (e.g., https://cheriot.org/) since you said CHERI, but just in case you did, or didn't necessarily mean to exclude it, they're building on (at least) a Diligent Arty A7-100T board (see https://cheriot.org/fpga/try/2023/11/16/cheriot-on-the-arty-a7.html && https://github.com/microsoft/cheriot-safe), specific part: XC7A100TCSG324-1.

minidracula fucked around with this message at 06:32 on May 8, 2024

karoshi
Nov 4, 2008

"Can somebody mspaint eyes on the steaming packages? TIA" yeah well fuck you too buddy, this is the best you're gonna get. Is this even "work-safe"? Let's find out!
There are also cheap smart NICs based on FPGAs being decommissioned by the cloud providers which you can find in ebay. Stuff like
https://www.ebay.com/itm/185659756161, https://www.ebay.com/itm/144113217470 and https://www.ebay.com/itm/275258652279. Some of those FPGAs are non-standard and you'll need to use the non-free vendor tools. It's quite a rabbit hole, but some very enthusiastic enthusiast have gotten some of those to work.

The altera/intel Arria parts have hard-FPUs (float32 MAC, IIRC) which can save you some resources, if you feel like integrating them into the upstream IP. :v: This would be specially useful for implementing GPUs.

minidracula
Dec 22, 2007

boo woo boo

karoshi posted:

There are also cheap smart NICs based on FPGAs being decommissioned by the cloud providers which you can find in ebay. Stuff like
https://www.ebay.com/itm/185659756161, https://www.ebay.com/itm/144113217470 and https://www.ebay.com/itm/275258652279. Some of those FPGAs are non-standard and you'll need to use the non-free vendor tools. It's quite a rabbit hole, but some very enthusiastic enthusiast have gotten some of those to work.

The altera/intel Arria parts have hard-FPUs (float32 MAC, IIRC) which can save you some resources, if you feel like integrating them into the upstream IP. :v: This would be specially useful for implementing GPUs.
And to think I was involved in one of the v1/v0 iterations of a thing that later led to Catapult...

Ceyton
Oct 9, 2004

YOU'RE DEAD ARMITAGE!
YOU'RE DEAD ARMITAGE!
YOU'RE DEAD ARMITAGE!

Subjunctive posted:

it’s OK

does anyone know what kind of FPGA you need to run the CHERI implementation?

A cheap dev kit with a Spartan 7 or Cyclone 10 will probably suffice.

If you really want to be sure you'll be able to fit the core(s) you want to try... I guess e-mail someone on the CHERI team and ask for the FPGA utilization numbers? I can't find that info published anywhere, though I highly doubt they used more than a tiny fraction of that (very big and expensive) Ultrascale+ device.

Subjunctive
Sep 12, 2006

✨sparkle and shine✨

Nice, thanks all. I don’t think I can mail the CHERI folks right now without embarrassing myself, but I found a promising YouTube channel to learn the basics.

https://youtube.com/@fpgasforbeginners?si=kI7Tv04zdqLcjha0

minidracula
Dec 22, 2007

boo woo boo
There's this WRT PPA for a specific build of cheriot-ibex (so CHERIoT, and not any of the CHERI-RISC-V designs built on top of Piccolo, Flute, or Tooba), but I wouldn't necessarily read much into this for CHERI-RISC-V, due to a bunch of variables:

quote:

Timing, area and power

A PPA study conducted at Microsoft shows that cheriot-ibex is similar to the original ibex design in terms of area and power, however with moderate increase in area.

cheriot-ibex (configured as 3-stage pipeline) has been synthesized successfully using Synopsys DC-topo at 250MHz using TSMC 28nm (28LP) libraries (ss 1.03v) and 550MHz using TSMC 5nm (N5) libraries (ss 0.6v). Timing is mostly limited by TCM read access time (which approaches 1.6ns in the N5 case).

The design area is ~60k gate equivalents (~25% more the original ibex design). Both dynamic and leakage power are shown as similar to the original ibex design.
I think I have some numbers for "stock" (non-CHERI) Piccolo, Flute, and Tooba cores laying around from some of my experiments, but not ready to hand. I'll see if I can find them, or maybe just do some fresh synthesis runs. Again, wouldn't necessarily tell you much re: CHERI, but would feasibly give you a reasonable lower bound for each, since CHERI's just gonna add more.

I'm willing to bet the VCU118 is an over-provisioned board & part in general too, sure, but I guess I don't know that. I mean, it's what I'd do. Especially for multiple different core designs. And they may have been using the same board for ISAv8 and prior ISA versions and/or ARM and/or previous MIPS work. That said, I did do some very brief quick & dirty searching to see if I could turn up utilization numbers, and didn't find any re: CHERI-Piccolo, CHERI-Flute, or CHERI-Tooba, on that board/part or another, but it was a brief and very surface level search, so I'll see if I can dig up better numbers later.

EDIT: OK, so I found some numbers while eating a late lunch microwaved freezer burrito:

quote:

Baseline Performance

PPA
Run the ./get_ppa.py script to get numbers measured by Vivado, for example:
code:
$ ./get_ppa.py vivado/soc_bluespec_p1/soc_bluespec_p1.runs/impl_1/
{"power_W": 0.25, "CLB_LUTs": 90341, "CLB_regs": 118324, "cpu_Mhz": 50.0}
Baseline values as of GFE 4.x release:
pre:
processor      power_W    CLB_LUTs    CLB_regs    cpu_Mhz
_________________________________________________________
Bluespec P1    0.25       90341       118324      50.0
Bluespec P2    0.302      121254      128260      100.0
Bluespec P3    0.365      343698      250477      25.0
Chisel P1      0.267      84043       113347      50.0
Chisel P2      0.457      131524      188846      100.0
Chisel P3      0.37       188629      156332      25.0
Source: https://github.com/CTSRD-CHERI/BESSPIN-GFE?tab=readme-ov-file#baseline-performance

You'll be helped out by this PDF from 2020 <https://github.com/CTSRD-CHERI/BESSPIN-GFE/blob/cambridge/GFE_Rel5.2_System_Description.pdf> which describes the hardware in some useful ways ("GFE", here, if you're wondering, stands for "Government Furnished Equipment"). For our uses re: the table above, pp. 4-5 serve as a decoder ring to make sure we know what "P1", "P2", "P3" -- whether prefixed by either Bluespec or Chisel -- mean in context: Bluespec P1 is CHERI-Piccolo, Bluespec P2 is CHERI-Flute, Bluespec P3 is CHERI-Tooba.

The same document shows what else is being instantiated on the UltraScale+ part, including supporting Xilinx IP (unsurprising).

minidracula fucked around with this message at 00:13 on May 9, 2024

Ceyton
Oct 9, 2004

YOU'RE DEAD ARMITAGE!
YOU'RE DEAD ARMITAGE!
YOU'RE DEAD ARMITAGE!

minidracula posted:

pre:
processor      power_W    CLB_LUTs    CLB_regs    cpu_Mhz
_________________________________________________________
Bluespec P1    0.25       90341       118324      50.0
Bluespec P2    0.302      121254      128260      100.0
Bluespec P3    0.365      343698      250477      25.0
Chisel P1      0.267      84043       113347      50.0
Chisel P2      0.457      131524      188846      100.0
Chisel P3      0.37       188629      156332      25.0

Oy, that's a lot bigger than I thought (I'm used to tiny in-order ARM stuff). You're gonna need to go well above entry level to get something that can fit even the small ones.

Xilinx Artix Ultrascale+ AU25P FPGA (141K LUTs, 282K regs) should be able to handle the Piccolos and mayyyyyybe the Flutes. Generally you shouldn't count on being able to go above 80% LUT/reg usage.

A relatively noob-friendly Opal Kelly devkit with that FPGA will set you back about $1200. The Tooooba cores will require at least one of the larger Kintex/Virtex Ultrascale FPGAs, and those will set you back a few thousand.

edit: the cheaper Artix-7 XC7A200T FPGA will probably work too, but beware of exchange rates between Ultrascale+ LUTs and 7-series LUTs. It would be nice if you had access to Vivado/Quartus so that you could do trial synthesis runs with different FPGAs and find the cheapest one that works. But if you don't have access to them through your work/school, non-locked-down licenses are not cheap

Ceyton fucked around with this message at 02:24 on May 9, 2024

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BobHoward
Feb 13, 2012

The only thing white people deserve is a bullet to their empty skull

Ceyton posted:

edit: the cheaper Artix-7 XC7A200T FPGA will probably work too, but beware of exchange rates between Ultrascale+ LUTs and 7-series LUTs. It would be nice if you had access to Vivado/Quartus so that you could do trial synthesis runs with different FPGAs and find the cheapest one that works. But if you don't have access to them through your work/school, non-locked-down licenses are not cheap

You can generate free Vivado licenses for "WebPack" Xilinx parts, AKA the devices small and cheap enough that they don't want the cost of tools to be a barrier to people designing with them. I don't remember if the XC7A200T is a WebPack part, though.

I don't think there's any significant difference between US+ and 7-series LUTs, btw? It's still a 6-input LUT architecture with roughly the same non-LUT resources. US+ routing and clock trees are much improved, though, makes timing closure much easier.

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