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if you're too bereft of vocabulary and must turn gauche to explain a simple concept you're not retreating from "too serious"
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Mar 13, 2015 22:05
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movax posted:fpga tooling on linux is only good for running headless builds imo; if you need to use the gui at all, stick with windows. linux is a second-class citizen (as it should be) headless builds should be the default
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Mar 13, 2015 22:06
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Poopernickel posted:it puts the P in PVT lol
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Mar 13, 2015 22:06
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Bloody posted:hope those opencores vhdl blocks work lol the other way
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Mar 13, 2015 22:06
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what's ur simulator? icarus?
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Mar 13, 2015 22:21
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karasu posted:of course it worked beautifully in simulation and even in my initial in hardware test. but let the FPGA get over 80 °C or configure the module in a certain way and yay total failure. spec commercial, not automotive, WONTFIX, WORKSINMYENVIRONMENT
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Mar 17, 2015 19:50
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video processing one mipi port? two cameras? wow, no way we could buy a mux, better slap a FPGA on there
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Mar 17, 2015 21:03
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the closest Real Thing to that is a bunch of pin-compatible parts from different micro lines, like a M0 and a M4 that can be reworked after layout
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Mar 17, 2015 21:51
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Bloody posted:i have a lookup table mapping 10-bit values to 9-bit values. every possible 10 bit input is accounted for. you would think that, given absolutely arbitrary 10-bit input, it would be utterly impossible to get a 9-bit output that does not exist in the table. why are there 9bit values that aren't in the table tho
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Mar 18, 2015 02:19
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let it take 2 cycles to look up and see if it still happens
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Mar 18, 2015 02:20
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Bloody posted:the baffling output is a completely invalid control character that the block's spitting out pretty reliably. is the bit wrong or the character is the bit calculated in any way separately from the rest does the byte predictably match any nearby byte in the stream
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Mar 18, 2015 06:35
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but you stored the old traces right? don't worry, it'll reproduce when you pull the shades up in the afternoon
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Mar 18, 2015 16:56
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he mentioned it, it's 8b/10b like in older gen PCIe. the 10b encodings are chosen to maintain DC balance on the line, the 9th bit is really just "it's not data, it's a COM/STP/SDP byte or other framing info" so there are a lot of values from 256-512 that you wouldn't ever expect to see
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Mar 18, 2015 17:05
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how is arduino forking or panelizing or however you call it when it's open hardware going
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Mar 31, 2015 08:04
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i2c is great but i'll never understand why every device datasheet has timing diagrams explaining the protocol like give me a register map and call it a day, there's no need to put the exact same timing diagrams on every single datasheet
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Apr 2, 2015 23:11
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you shouldn't be bit banging it anyway "hey HW module on this mcu, talk to address X, write data Z to register Y then read register Q" if you can't tell if it's a 7/8 bit address by looking at it idgaf
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Apr 2, 2015 23:52
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Bloody posted:lvds spi that smiley with the eyeballs
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Apr 3, 2015 00:52
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DuckConference posted:we're doing our next product with an stm32f4, and since Kiel uvision 4 kind of sucks, it looks like we might go with gcc/eclipse/openocd. it's not a horrible idea is it? movax posted:vivado / xilinx still doesn't understand the concept of people wanting to version control stuff though.
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Apr 7, 2015 18:26
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movax posted:so in a vivado zynq design, you can do a block design to easily stitch together axi peripherals and stuff lmao oic c# does some of that with autogenerated files from the GUI designer, but i haven't had to merge too many of those just do pure verilog imho
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Apr 7, 2015 18:49
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i thought TI's CCS eclipse skin was perfectly serviceable. even atmel's VS skin is decent enough just drives me crazy when the Cube won't spit out a gcc-compatible BSP, or atmel's eval kit demo programs are written to IAR instead of their own tooling seems time to mention i'm also looking for my next job, so if y'all need a verilogger or firmware dev hit me up
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Apr 7, 2015 18:58
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Bloody posted:we're definitely hiring your type, where do you live and/or are you interested in relocating to boston area Fanged Lawn Wormy posted:i'm getting interested in taking the arduino training wheels off and using big boy developer tools for embedded systems that said, light blue bean is easier than arduino (literally program from your iPhone), then arduino, then these folks are a step up i'm inclined to second guess the supposition that your work isn't limited by arduino. it might be the case, or you might be solving problems inefficiently because of your limited tool set? a lot of embedded work is power saving, if you're always plugged into the wall it might be interesting to try to break that dependency, learn how to write to the flash segments and use a USB power brick to walk around with it
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Apr 8, 2015 01:02
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never understood the fixation some people have on linker scripts and make files. you've got C and asm, and a bunch of knobs to fix the translation between them. becoming an expert knob maker doesn't help the final product as much as a half dozen easier things
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Apr 8, 2015 19:37
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yeah im pretty good once it's in assembly or talking about memory, i guess that's my blind spot here still kills me to see college programs teaching makefiles before hello world, but w/e
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Apr 8, 2015 21:25
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Mr Dog posted:Open the binary ROM image in a hex editor and gaze upon your work. Every byte of it is yours. why aren't we pushing people to make their own flex/bison files for their C dialect? why not their own parser generator? what makes chucking more files at GCC some magical point that's Totally Real where an IDE isn't Mr Dog posted:Then learn the joys of gdb remote debugging and double and triple-checking your clock setup and GPIO port configuration code when you run the poo poo and the GPIO didn't start blinking like it was supposed to
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Apr 8, 2015 21:37
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hobbesmaster posted:sadly i'm now curious to see whether that would actually work Mido posted:the ARM tools for eclipse have makefile generators that you can specify architectures for and overall it Just Works, even better if your mfg of choice has their own eclipsey plugins that will do their own linker script generation and generate boilerplate driver stuff for your SoC like interacting with the DMA engine or generating startup code for things like clocking changes you can wrap in a state machine really thought i spent 8 years in the silicon mines and ive got a pretty good grasp on what HW's doing
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Apr 8, 2015 21:50
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i wanna put iHDL and protocyte on my resume to see if anyone can come up with a whiteboard problem across two dead languages
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Apr 9, 2015 15:53
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hobbesmaster posted:interview question: "if you were to interview a candidate with two dead languages on their resume what would you ask them?" those two? "why was domino logic natively supported?" and "why was the threading model for checkers utterly broken?"
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Apr 9, 2015 18:42
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eschaton posted:I wonder if, 10 years from now, the FPGA environments will all be local web garbage running in an app shell and written with node.js cadence is offering something like that upload your verilog & test bench, they'll run it for you and you can check results on a dashboard on the one hand i'd absolutely love to chuck a random SW instance onto a new HW design and just hear back if it was a pass/fail, over here in reality i know it'd devolve into trying to debug some goofy bullshit at arm's length BobHoward posted:how do you feel about mountain view and/or satan clara
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May 1, 2015 02:10
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ok, starting to dig into fabscalar, which generates parameterized superscalar cores i have an atlys2 board, had to download the old ISE to compile for it. i have dummy projects compiling, starting to feed the fabscalar stuff into it. the fpga shims aren't released yet, so my first shot at compiling it took an hour for it to figure out every bit was unnecessary and produce a .bit file with zero gates so i need that shim. before that, i ought to be able to simulate the thing. i don't have ncvlog that it's assuming, so i grabbed icarus verilog thinking it would do just fine in simulation. it's failing on a concatenation where they do an inline addition in the decoder: code:
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May 6, 2015 07:06
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lol trick question everything is poo poo i actually did the tmp var to shave off a bit that night. a couple hours later after getting the verilog built (there were some other minor issues with it being over-pedantic) I wasn't able to get the VPI stuff compiled or linked or whatever you'd call that. tried importing the g++ built lib, tried compiling from source with the icarus VPI compiler, nothing really clicked it wouldn't be too bad starting a new design, but i'm taking a legacy code base without support and i haven't been able to recreate the simulation they did with ncvlog. I'm assuming ncvlog is the kind of tool every uni has an install kicking around so there's no need for icarus support from this particular team
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May 7, 2015 14:14
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i've got the fabscalar simulator 1 file away from working. the specific failure is: ../../libss-vpi/lib.src/misc.cc:84:3: error: C-style cast from 'char **' to 'va_list' (aka '__builtin_va_list') is not allowed so a dodgy cast in the command line parsing section of the C code being compiled to be called from the simulated HDL is why i can't get this thing built does haskell lend itself to pipelining?
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May 9, 2015 22:06
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Mido posted:edit: yes $60/hr is really really low  srsly, 3x that i've got this thing compiled, built, linked, w/e, it's up and running and failing trying to load the checkpoint data. it smells like a size/alingnment/endianness thing, have to comb through the symbols & changes to see what I broke
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May 10, 2015 17:28
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lol "bettery holder"
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May 13, 2015 16:17
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Mido posted:that's cool depending on the characteristics of the data channels and what the data is no you've got enough horsepower to manage a BTLE stack, that sets a lower bound on the peripheral compute capability. now you've got a 20b/s (spec is 35KB/s thru, but that's in an EMI chamber with full control of when packets/notifications are sunk) channel out to something a few orders of magnitude better, and from there if latency is not important you're punting to essentially infinite resources in the cloud stopping at the phone is almost never going to be the right answer
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May 19, 2015 20:48
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async clock crossing is sweet, one of those concepts that took 1.5 passes for me to understand gray codes, bubble gaps, its all p. neat
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Jun 15, 2015 00:36
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it's not that hard if you don't care about determinism, there's a head/tail pointer encoded w/ gray code so it doesn't matter if a signal from one domain doesn't settle by the time the other samples it you end up with bubbles and one of the interfaces probably has to be capable of backpressure omg flow control credits negotiated during link training
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Jun 15, 2015 01:05
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Bloody posted:current best candidate seems to be slapping either a lovely standalone radio like one of the nordic chips with a micro that does everything else or one of these bluetooth soc chips with a lovely standalone dac but neither option is appealing what's the use case? do you want something like a rn52?
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Jun 16, 2015 07:56
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variac?
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Jun 17, 2015 01:13
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do you need a little structure around $display calls or do you have the flexibility to pull in something like OVM
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Jun 22, 2015 08:08
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| # ¿ May 3, 2024 11:21 |
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http://electronics.stackexchange.com/questions/71223/is-there-a-way-of-conditionally-triggering-a-compile-time-error-in-verilog like that?
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Jun 22, 2015 08:32
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